component

EFM32G232F128G-E-QFP64

Public Made by Adom

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SILICON LABS SILICON LABS, QFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersefm32g232f128g-e-qfp64factory-2.0.0extractor-text

Verified EFM32G232F128G-E-QFP64

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier lcsc, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: EFM32G232F128G-E-QFP64 · QFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 205-page datasheet
  • ✓distributor: lcsc C430023, digikey 336-5327-ND, mouser 634-32G232F128GEFP64
  • ✓family: LQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-lyyvy3c2/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: body within the datasheet's package drawing (datasheet p.176)
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 76 kB, viewers/symbol.html 41 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ efm32g232f128g-e-qfp64.kicad_sym✓ efm32g232f128g-e-qfp64.kicad_mod✓ efm32g232f128g-e-qfp64.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
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efm32g232f128g-e-qfp64 / README.md
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Ray Publish 0.1.0 a6a369e

EFM32G232F128G-E-QFP64

SILICON LABS · SILICON LABS · QFP-64(10x10)

EFM32G232F128G-E-QFP64 from SILICON LABS, in a QFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional GPIO PA0 with alternate functions TIM0_CC0 #0/1 and I2C0_SDA #0.
2 PA1 bidirectional GPIO PA1 with alternate functions TIM0_CC1 #0/1, I2C0_SCL #0 and CMU_CLK1 #0.
3 PA2 bidirectional GPIO PA2 with alternate functions TIM0_CC2 #0/1 and CMU_CLK0 #0.
4 PA3 bidirectional GPIO PA3 with alternate function TIM0_CDTI0 #0.
5 PA4 bidirectional GPIO PA4 with alternate function TIM0_CDTI1 #0.
6 PA5 bidirectional GPIO PA5 with alternate functions TIM0_CDTI2 #0 and LEU1_TX #1.
7 IOVDD_0 power_in Digital IO power supply 0.
8 VSS power_in Ground.
9 PC0 bidirectional GPIO PC0 with ACMP0_CH0, PCNT0_S0IN #1 and US1_TX #1.
10 PC1 bidirectional GPIO PC1 with ACMP0_CH1, PCNT0_S1IN #1 and US1_RX #1.
11 PC2 bidirectional GPIO PC2 with ACMP0_CH2 and US1_CLK #1.
12 PC3 bidirectional GPIO PC3 with ACMP0_CH3 and US1_CS #1.
13 PC4 bidirectional GPIO PC4 with ACMP0_CH4, LETIM0_OUT0 #3, PCNT1_S0IN #0 and US2_CLK #0.
14 PC5 bidirectional GPIO PC5 with ACMP0_CH5, LETIM0_OUT1 #3, PCNT1_S1IN #0 and US2_CS #0.
15 PB7 bidirectional GPIO PB7 with LFXTAL_P (low frequency crystal positive pin) and US1_CLK #0.
16 PB8 bidirectional GPIO PB8 with LFXTAL_N (low frequency crystal negative pin) and US1_CS #0.
17 PA8 bidirectional GPIO PA8 with alternate function TIM2_CC0 #0.
18 PA9 bidirectional GPIO PA9 with alternate function TIM2_CC1 #0.
19 PA10 bidirectional GPIO PA10 with alternate function TIM2_CC2 #0.
20 RESETn input Reset input, active low; drive low only during reset and let the internal pull-up release it.
21 PB11 bidirectional GPIO PB11 with DAC0_OUT0 and LETIM0_OUT0 #1.
22 VSS power_in Ground.
23 AVDD_1 power_in Analog power supply 1.
24 PB13 bidirectional GPIO PB13 with HFXTAL_P (high frequency crystal positive pin) and LEU0_TX #1.
25 PB14 bidirectional GPIO PB14 with HFXTAL_N (high frequency crystal negative pin, also optional external clock input) and LEU0_RX #1.
26 IOVDD_3 power_in Digital IO power supply 3.
27 AVDD_0 power_in Analog power supply 0.
28 PD0 bidirectional GPIO PD0 with ADC0_CH0, PCNT2_S0IN #0 and US1_TX #1.
29 PD1 bidirectional GPIO PD1 with ADC0_CH1, TIM0_CC0 #3, PCNT2_S1IN #0 and US1_RX #1.
30 PD2 bidirectional GPIO PD2 with ADC0_CH2, TIM0_CC1 #3 and US1_CLK #1.
31 PD3 bidirectional GPIO PD3 with ADC0_CH3, TIM0_CC2 #3 and US1_CS #1.
32 PD4 bidirectional GPIO PD4 with ADC0_CH4 and LEU0_TX #0.
33 PD5 bidirectional GPIO PD5 with ADC0_CH5 and LEU0_RX #0.
34 PD6 bidirectional GPIO PD6 with ADC0_CH6, LETIM0_OUT0 #0 and I2C0_SDA #1.
35 PD7 bidirectional GPIO PD7 with ADC0_CH7, LETIM0_OUT1 #0 and I2C0_SCL #1.
36 PD8 bidirectional GPIO PD8 with alternate function CMU_CLK1 #1.
37 PC6 bidirectional GPIO PC6 with ACMP0_CH6, LEU1_TX #0 and I2C0_SDA #2.
38 PC7 bidirectional GPIO PC7 with ACMP0_CH7, LEU1_RX #0 and I2C0_SCL #2.
39 VDD_DREG power_in Power supply for on-chip voltage regulator.
40 DECOUPLE power_out Decouple output for on-chip voltage regulator; an external capacitance of size CDECOUPLE is required at this pin.
41 PC8 bidirectional GPIO PC8 with ACMP1_CH0, TIM2_CC0 #2 and US0_CS #2.
42 PC9 bidirectional GPIO PC9 with ACMP1_CH1, TIM2_CC1 #2 and US0_CLK #2.
43 PC10 bidirectional GPIO PC10 with ACMP1_CH2, TIM2_CC2 #2 and US0_RX #2.
44 PC11 bidirectional GPIO PC11 with ACMP1_CH3 and US0_TX #2.
45 PC12 bidirectional GPIO PC12 with ACMP1_CH4 and CMU_CLK0 #1.
46 PC13 bidirectional GPIO PC13 with ACMP1_CH5, TIM0_CDTI0 #1/3, TIM1_CC0 #0 and PCNT0_S0IN #0.
47 PC14 bidirectional GPIO PC14 with ACMP1_CH6, TIM0_CDTI1 #1/3, TIM1_CC1 #0 and PCNT0_S1IN #0.
48 PC15 bidirectional GPIO PC15 with ACMP1_CH7, TIM0_CDTI2 #1/3, TIM1_CC2 #0 and DBG_SWO #1.
49 PF0 bidirectional GPIO PF0 with LETIM0_OUT0 #2 and DBG_SWCLK #0/1 (debug clock input enabled out of reset, built-in pull down).
50 PF1 bidirectional GPIO PF1 with LETIM0_OUT1 #2 and DBG_SWDIO #0/1 (debug data enabled out of reset, built-in pull up).
51 PF2 bidirectional GPIO PF2 with ACMP1_O #0 and DBG_SWO #0 (serial wire viewer output, not enabled after reset).
52 PF3 bidirectional GPIO PF3 with alternate function TIM0_CDTI0 #2.
53 PF4 bidirectional GPIO PF4 with alternate function TIM0_CDTI1 #2.
54 PF5 bidirectional GPIO PF5 with alternate function TIM0_CDTI2 #2.
55 IOVDD_5 power_in Digital IO power supply 5.
56 VSS power_in Ground.
57 PE8 bidirectional GPIO PE8 with alternate function PCNT2_S0IN #1.
58 PE9 bidirectional GPIO PE9 with alternate function PCNT2_S1IN #1.
59 PE10 bidirectional GPIO PE10 with TIM1_CC0 #1, US0_TX #0 and BOOT_TX (bootloader transmit).
60 PE11 bidirectional GPIO PE11 with TIM1_CC1 #1, US0_RX #0 and BOOT_RX (bootloader receive).
61 PE12 bidirectional GPIO PE12 with TIM1_CC2 #1 and US0_CLK #0.
62 PE13 bidirectional GPIO PE13 with US0_CS #0 and ACMP0_O #0.
63 PE14 bidirectional GPIO PE14 with alternate function LEU0_TX #2.
64 PE15 bidirectional GPIO PE15 with alternate function LEU0_RX #2.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -40 150 °C 29
Maximum soldering temperature TS 260 °C Latest IPC/JEDEC J-STD-020 Standard 29
External main supply voltage VDDMAX 0 3.8 V 29
Voltage on any I/O pin (max is VDD+0.3) VIOPIN -0.3 V 29
Current per I/O pin (sink) IIOMAX_SINK 100 mA 29
Current per I/O pin (source) IIOMAX_SOURCE -100 mA 29
Ambient temperature range TAMB -40 85 °C 29
Operating supply voltage VDDOP 1.98 3.8 V 29
Internal APB clock frequency fAPB 32 MHz 29
Internal AHB clock frequency fAHB 32 MHz 29
EM0 current IEM0 181 206 µA/MHz 28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 30
EM0 current IEM0 183 207 µA/MHz 21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 30
EM0 current IEM0 185 211 µA/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 30
EM0 current IEM0 186 215 µA/MHz 11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 30
EM0 current IEM0 191 218 µA/MHz 6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 30
EM1 current IEM1 47 62 µA/MHz 28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 30
EM1 current IEM1 50 69 µA/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 30
EM1 current IEM1 56 83 µA/MHz 6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 30
EM2 current IEM2 0.9 1.5 µA RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=25 ºC 30
EM2 current IEM2 3 6 µA RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=85 ºC 30
EM3 current IEM3 0.59 1 µA VDD= 3.0 V, TAMB=25 ºC 30
EM3 current IEM3 2.75 5.8 µA VDD= 3.0 V, TAMB=85 ºC 30
EM4 current IEM4 0.02 0.045 µA VDD= 3.0 V, TAMB=25 ºC 30
EM4 current IEM4 0.25 0.7 µA VDD= 3.0 V, TAMB=85 ºC 30
BOD threshold on falling external supply voltage VBODextthr- 1.74 1.96 V EM0 40
Power-on Reset threshold on rising external supply voltage VPORthr+ 1.98 V 40
Negative pulse length to ensure complete reset tRESET 50 ns 40
Flash erase cycles before failure ECFLASH 20000 cycles 41
Flash data retention RETFLASH 10 years TAMB<85 ºC 41
Word (32-bit) programming time tW_PROG 20 µs 41
Page erase time tP_ERASE 20.7 22 24.8 ms 41
Device erase time tD_ERASE 41.8 45 49.2 ms 41
Erase current IERASE 7 mA Measured at 25 °C 41
Write current IWRITE 7 mA Measured at 25 °C 41
Supply voltage during flash erase and write VFLASH 1.98 3.8 V 41
Input leakage current IIOLEAK 0.1 40 nA High Impedance IO connected to GROUND or VDD 43
Pulse width removed by glitch suppression filter tIOGLITCH 10 50 ns 43
Supported crystal ESR ESRLFXO 30 120 kOhm 50
Supported crystal external load range CLFXOL 25 pF 50
HFXO supported nominal crystal frequency fHFXO 4 32 MHz 51
LFRCO oscillation frequency fLFRCO 31.29 32.768 34.24 kHz VDD= 3.0 V, TAMB=25°C 52
HFRCO oscillation frequency fHFRCO 27.16 28 28.84 MHz 28 MHz frequency band, VDD= 3.0 V, TAMB=25 ºC 53
HFRCO oscillation frequency fHFRCO 13.58 14 14.42 MHz 14 MHz frequency band, VDD= 3.0 V, TAMB=25 ºC 53
HFRCO current consumption IHFRCO 99 120 µA fHFRCO = 14 MHz 53
HFRCO duty cycle DCHFRCO 48.5 50 51 % fHFRCO = 14 MHz 53
ULFRCO oscillation frequency fULFRCO 0.7 1.75 kHz 25 °C, 3 V 57
ADC fADCCLK fADCCLK 13 MHz BIASPROG=0xF4B 59
ADC offset voltage VADCOFFSET -4 0.3 4 mV After calibration, differential 65
ADC differential non-linearity DNLADC -1 0.7 4 LSB VDD= 3.0 V, external 2.5 V reference 65
ADC integral non-linearity INLADC -3 1.2 3 LSB VDD= 3.0 V, external 2.5 V reference, end point method 65
ADC VREF voltage VREF 1.2 1.25 1.3 V 1.25 V reference 65
ADC VREF voltage VREF 2.4 2.5 2.6 V 2.5 V reference 65
DAC load current ILOAD_DC 11 mA 72
ACMP offset voltage VACMPOFFSET -12 0 12 mV BIASPROG= 0b1010, FULLBIAS=0 and HALFBIAS=0 in ACMPn_CTRL register 73
LCD supply voltage range VLCD 2 3.8 V Internal boost circuit enabled 76
Voltage regulator decoupling capacitor CDECOUPLE 1 µF X5R capacitor recommended. Apply between DECOUPLE pin and GROUND 40
LFRCO temperature coefficient TCLFRCO 0.02 %/°C 52

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts gold The TQFP64 Package is 10 by 10 mm in size and has a 0.5 mm pin pitch. The TQFP64 Package uses Nickel-Palladium-Gold preplated leadframe. 176

CAD (KiCad official)

  • Symbol: EFM32G232F128G-E-QFP64
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: QFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: efm32g232f128g-e-qfp64-etched.step / efm32g232f128g-e-qfp64-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efm32g232f128g-e-qfp64.step / efm32g232f128g-e-qfp64.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (205 pp, sha256 1201f60cf3c01dda, retrieved 2026-11-13, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF