EDA Bridge Standard: one way for an AI to drive every PCB tool

[
 {
  "name": "sch_connect_pins",
  "tier": "core",
  "summary": "Wire pins to pins on a sheet by Ref.Pin: an L-shaped route (one horizontal and one vertical leg) for each pair, with a junction dot wherever a route meets an existing wire in a T. One undo step.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "pairs": "[{from: \"U1.1\", to: \"R5.2\", first?: h|v (the leg to draw first; default along the axis the from pin points), via?: [[x, y], ...] mm waypoints}] (required)",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "wired": "int",
   "routes": "[{from, to, points: [[x, y]], ids: [wire id]}]",
   "junctionsAdded": "[[x, y]]",
   "failed": "[{from, to, error}]",
   "saved": "bool"
  },
  "hint": "Pins are matched by number, then by name. Aligned pins get one straight wire; otherwise the route turns once. Check the result with sch_pins (connectedPins) or run_erc.",
  "pitfalls": [
   "The route does not avoid part bodies or other wires: a leg running along another wire merges the two nets. Steer with first or via, and check with sch_pins."
  ],
  "related": [
   "sch_pins",
   "sch_connect",
   "sch_delete_wire",
   "run_erc"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "pairs": [
    {
     "from": "U1.1",
     "to": "R2.1"
    },
    {
     "from": "U1.2",
     "to": "C3.1",
     "first": "v"
    }
   ]
  },
  "longRunning": true,
  "timeoutSeconds": 120,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_connect_to_bus",
  "tier": "core",
  "summary": "Fan pins onto a bus: for each pin a wire running to the bus, a 45-degree bus entry onto it and a member label (D0, D1 ...) on the wire. One undo step.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "pins": "[\"U1.1\", \"U1.2\"] Ref.Pin, in member order (required)",
   "bus": "id of the bus segment (default the only bus on the sheet)",
   "members": "[\"D0\", \"D1\"]: the member names in pin order",
   "prefix": "\"D\": or name members prefix + number",
   "start": "int, default 0: the first number with prefix",
   "entry": "up|down (a vertical bus) or left|right (a horizontal bus): the way the entries lean",
   "busLabel": "\"D[0..7]\": also label the bus",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "connected": "[{pin, member, wireId, entryId}]",
   "busLabel": "string or null",
   "failed": "[{pin, error}]",
   "saved": "bool"
  },
  "hint": "Members name the nets: members lists them in pin order, or prefix plus start counts up. Refused with entry_off_bus when an entry would miss the bus: extend the bus with sch_bus first.",
  "pitfalls": [
   "Pins should face the bus; a pin facing away gets a wire across its own part.",
   "Two pins at the same height on a vertical bus share an entry point and collide: offset them or lean the entries differently."
  ],
  "related": [
   "sch_bus",
   "sch_bus_entry",
   "sch_pins"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "pins": [
    "U1.1",
    "U1.7"
   ],
   "prefix": "D",
   "busLabel": "D[0..1]"
  },
  "longRunning": true,
  "timeoutSeconds": 120,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_junction",
  "tier": "core",
  "summary": "Add junction dots at points, or remove dots by id or point. One undo step.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "points": "[[x, y], ...] mm: where to add dots",
   "remove": "[id or [x, y], ...]: dots to remove",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "added": "[{id, at}]",
   "removed": "[id]",
   "skipped": "[[x, y]]: points that already had a dot",
   "notNeeded": "[[x, y]]: added dots where fewer than three items meet (legal, but they join nothing extra)",
   "saved": "bool"
  },
  "hint": "The wiring verbs add the dots they need on their own; use this for a T made by hand, or to clean up.",
  "pitfalls": [
   "Items join only where their coordinates match exactly: use pin ends from sch_pins, or points on the sheet's grid."
  ],
  "related": [
   "sch_items",
   "sch_split_wire",
   "sch_delete_wire"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "points": [
    [
     110.49,
     60.96
    ]
   ]
  },
  "longRunning": true,
  "timeoutSeconds": 120,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_bus",
  "tier": "core",
  "summary": "Draw a bus as a polyline (one bus segment per pair of points), optionally with a bus label such as D[0..7] or a group {SDA SCL} at its first point. One undo step.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "points": "[[x, y], [x, y], ...] mm (required)",
   "label": "\"D[0..7]\" or \"{SDA SCL}\": the nets the bus carries",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "ids": "[bus segment id]",
   "label": "{id, text} or null",
   "saved": "bool"
  },
  "hint": "A bus carries the nets its label names, and each member wire needs its own label. sch_connect_to_bus does the member wires, entries and labels for a set of pins.",
  "pitfalls": [
   "A bus with no label carries nothing: ERC reports its members as unconnected."
  ],
  "related": [
   "sch_bus_entry",
   "sch_connect_to_bus",
   "sch_delete_wire",
   "sch_items"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "points": [
    [
     203.2,
     50.8
    ],
    [
     203.2,
     101.6
    ]
   ],
   "label": "D[0..7]"
  },
  "longRunning": true,
  "timeoutSeconds": 120,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_bus_entry",
  "tier": "core",
  "summary": "Add 45-degree bus entries: the short diagonal that joins a member wire's end to a bus. One undo step.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "entries": "[{at: [x, y] mm (the wire end), direction: up-right|down-right|up-left|down-left as seen (default down-right)}] (required)",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "added": "[{id, at, end: [x, y] (the bus side), onBus: bool}]",
   "saved": "bool"
  },
  "hint": "end is the bus side of each entry; onBus says whether it lands on a bus segment.",
  "pitfalls": [
   "The bus side must touch a bus and the other end a wire end, exactly, or ERC reports the entry as unconnected."
  ],
  "related": [
   "sch_bus",
   "sch_connect_to_bus",
   "sch_items"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "entries": [
    {
     "at": [
      200.66,
      63.5
     ],
     "direction": "up-right"
    }
   ]
  },
  "longRunning": true,
  "timeoutSeconds": 120,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_split_wire",
  "tier": "core",
  "summary": "Split the wire through a point into two wires there, with a junction dot at the cut, so a new branch can end on a wire end. One undo step.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "at": "[x, y] mm on the sheet (the tool's sheet origin, y up) (required)",
   "id": "the wire's id, when several wires pass through the point",
   "junction": "bool, default true",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "ids": "[first half (keeps the wire's id), second half (new id)]",
   "junction": "{id, at} or null",
   "saved": "bool"
  },
  "hint": "Split a wire where a new branch should join it, then wire to the cut.",
  "pitfalls": [
   "The point must lie on the wire and not at either end (not_on_wire otherwise)."
  ],
  "related": [
   "sch_delete_wire",
   "sch_junction",
   "sch_items"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "at": [
    110.49,
    60.96
   ]
  },
  "longRunning": true,
  "timeoutSeconds": 120,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_delete_wire",
  "tier": "core",
  "summary": "Delete wires or bus segments by id, by their two ends, or every wire through a point, and remove junction dots that no longer join three or more items. One undo step.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "ids": "[wire id, ...]",
   "from": "[x, y] mm, with to: the wire with exactly these ends (either order)",
   "to": "[x, y] mm",
   "at": "[x, y] mm: every wire passing through the point",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "deleted": "[{id, from, to}]",
   "junctionsRemoved": "[[x, y]]",
   "saved": "bool"
  },
  "hint": "Read ids with sch_items. from/to matches one segment, not a whole route.",
  "pitfalls": [
   "A polyline drawn in the editor is several wires sharing ends: from/to names one segment of it."
  ],
  "related": [
   "sch_items",
   "sch_split_wire",
   "sch_junction",
   "sch_connect_pins"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "from": [
    100.33,
    60.96
   ],
   "to": [
    120.65,
    60.96
   ]
  },
  "longRunning": true,
  "timeoutSeconds": 120,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_edit_label",
  "tier": "core",
  "summary": "Edit net labels: rotate, move to a point or by a delta, rename, or move every label of a net at once. One undo step.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "edits": "[{id | text (with at?: [x, y] to pick one) | net (every label of the net), rotation?: 0|90|180|270, to?: [x, y] mm (one label only), by?: [dx, dy] mm, rename?: string}] (required)",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "edited": "[{id, text, at, rotation}]",
   "failed": "[{edit, error}]",
   "saved": "bool"
  },
  "hint": "text picks every label with that text (or the one at at); net picks every label of the net. Read ids with sch_items.",
  "pitfalls": [
   "A label joins a net only where it sits on a wire or a pin end: moving it off disconnects it.",
   "rename changes only the labels picked: other labels with the old name stay on the old net."
  ],
  "related": [
   "sch_items",
   "sch_connect",
   "sch_edit"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "edits": [
    {
     "net": "VOUT",
     "by": [
      0,
      2.54
     ]
    }
   ]
  },
  "longRunning": true,
  "timeoutSeconds": 120,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_move_region",
  "tier": "core",
  "summary": "Move everything inside a box by (dx, dy): parts, wire ends inside the box (wires crossing its edge stretch), labels, junctions, no-connect markers, texts, bus entries and sheet symbols. One undo step.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "box": "[x1, y1, x2, y2] mm (required)",
   "by": "[dx, dy] mm (required)",
   "wires": "bool, default true: move wires, buses and bus entries",
   "labels": "bool, default true: move labels and texts",
   "junctions": "bool, default true: move junctions and no-connect markers",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "moved": "{parts, wires, buses, busEntries, labels, texts, junctions, noConnects, sheets: [id]}",
   "saved": "bool"
  },
  "hint": "Parts move by their anchor point. Move by a pure dx or a pure dy to keep stretched wires straight.",
  "pitfalls": [
   "A wire with one end in the box stretches diagonally when dx and dy are both non-zero.",
   "Keep the move on the sheet's grid, or pins and wires stop meeting.",
   "A multi-part component whose parts sit on both sides of the edge splits up."
  ],
  "related": [
   "sch_edit",
   "sch_items"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "box": [
    90,
    40,
    160,
    120
   ],
   "by": [
    25.4,
    0
   ]
  },
  "longRunning": true,
  "timeoutSeconds": 120,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_text",
  "tier": "core",
  "summary": "Add free text to a sheet (a note, a title, a design comment) with size, angle, justification, bold and italic. Text has no electrical meaning. One undo step.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "texts": "[{text, at: [x, y] mm, rotation?: 0|90|180|270, sizeMm?: 1.27, justify?: \"left bottom\", bold?: false, italic?: false}] (required)",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "added": "[{id, text, at}]",
   "saved": "bool"
  },
  "hint": "Net names are labels, not text: use sch_connect for them. Newlines in text become line breaks.",
  "pitfalls": [],
  "related": [
   "sch_items",
   "sch_edit_label"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "texts": [
    {
     "text": "USB input stage",
     "at": [
      50.8,
      30.48
     ],
     "sizeMm": 2.54,
     "bold": true
    }
   ]
  },
  "longRunning": true,
  "timeoutSeconds": 120,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_page",
  "tier": "core",
  "summary": "Read or set a sheet's page: paper size, orientation and title block (title, date, revision, company, comment lines).",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "paper": "A5 to A0, A to E, USLetter, USLegal, USLedger or custom",
   "orientation": "portrait|landscape",
   "widthMm": "number (custom paper)",
   "heightMm": "number (custom paper)",
   "title": "string",
   "date": "string",
   "rev": "string",
   "company": "string",
   "comments": "[string]: comment lines in order",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "paper": "string",
   "widthMm": "number",
   "heightMm": "number",
   "orientation": "string",
   "titleBlock": "{title, date, rev, company, comments}",
   "changed": "bool",
   "saved": "bool"
  },
  "hint": "With no change arguments it only reads. An empty string removes a title-block field. Each sheet of a hierarchy has its own page.",
  "pitfalls": [
   "Shrinking the paper moves nothing: items outside the new frame stay where they are (render_schematic shows it)."
  ],
  "related": [
   "sch_create",
   "render_schematic"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "paper": "A3",
   "title": "Main board",
   "rev": "B"
  },
  "longRunning": false,
  "timeoutSeconds": 30,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_items",
  "tier": "core",
  "summary": "List a sheet's wiring items with ids and coordinates: wires, buses, bus entries, net labels (local, global, hierarchical), power ports, junctions, no-connect markers, texts and sheet symbols. Read only.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "kinds": "[wires, buses, busEntries, labels, powerPorts, junctions, noConnects, texts, sheets] (default all)"
  },
  "output": {
   "wires": "[{id, from, to}]",
   "buses": "[{id, from, to}]",
   "busEntries": "[{id, at, end}]",
   "labels": "[{id, text, kind: local|global|hierarchical, at, rotation}]",
   "powerPorts": "[{id, net, at}]",
   "junctions": "[{id, at}]",
   "noConnects": "[{id, at}]",
   "texts": "[{id, text, at}]",
   "sheets": "[{id, name, file, at, sizeMm}]",
   "counts": "{kind: int}"
  },
  "hint": "The ids feed sch_delete_wire, sch_edit_label, sch_junction and sch_edit. Parts are in schematic_data.",
  "pitfalls": [
   "A wire is one straight segment: a polyline drawn in the editor is several wires sharing ends."
  ],
  "related": [
   "schematic_data",
   "sch_pins",
   "sch_delete_wire",
   "sch_edit_label"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "kinds": [
    "wires",
    "labels"
   ]
  },
  "longRunning": false,
  "timeoutSeconds": 30,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_pins",
  "tier": "core",
  "summary": "Every pin of the named parts on a sheet: its absolute position (rotation and mirror applied), number, name, electrical type, the side it leaves the body, and the wires, labels and nets touching it. Read only.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "references": "[\"U1\", \"R5\"] (default every part)",
   "connections": "bool, default true: add what touches each pin"
  },
  "output": {
   "pins": "[{ref, number, name, type, at: [x, y], direction: right|left|up|down as seen, hidden, touching: [{kind, id}], nets: [string], connectedPins: [Ref.Pin]}]"
  },
  "hint": "at is where a wire or label must land on the pin. connectedPins lists the other pins on the same copper on this sheet.",
  "pitfalls": [
   "Nets here come from this sheet's wires and labels only: netlist gives the project-wide nets.",
   "Hidden power pins (hidden:true) connect by name, not by wire."
  ],
  "related": [
   "sch_connect_pins",
   "sch_connect",
   "schematic_data",
   "netlist"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "references": [
    "U1",
    "R5"
   ]
  },
  "longRunning": false,
  "timeoutSeconds": 30,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_trace_point",
  "tier": "core",
  "summary": "Everything electrically connected at a point on a sheet: the wires, labels, pins, junctions, sheet pins and no-connect markers there, and for each net they belong to the whole net with its name. Read only.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "at": "[x, y] mm on the sheet (the tool's sheet origin, y up) (required)",
   "toleranceMm": "number, default 0.05"
  },
  "output": {
   "items": "[{kind, id, at}]",
   "nets": "[{name, pins: [Ref.Pin], labels, powerPorts, wires, leavesSheet: bool}]",
   "crossingWithoutJunction": "bool: two wires cross here without connecting",
   "nearest": "[x, y]: the nearest connectable point, when nothing is within tolerance"
  },
  "hint": "Read with the tool's own rules: wire ends join wires and wire middles (a T), labels and junction dots join a wire anywhere along it, pins join wire ends.",
  "pitfalls": [
   "One sheet only: a net that leaves through a global, hierarchical or power label (leavesSheet:true) continues on other sheets. netlist gives the compiled net."
  ],
  "related": [
   "sch_pins",
   "net_connections",
   "netlist"
  ],
  "example": {
   "sheet": "C:/proj/Power.SchDoc",
   "at": [
    109.22,
    73.66
   ]
  },
  "longRunning": false,
  "timeoutSeconds": 30,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_hierarchy",
  "tier": "core",
  "summary": "The sheet tree of a design, recursively: each sheet's name, file, id, instance path, page number, position, size and pins. renumber:true renumbers pages depth-first from the root.",
  "input": {
   "sheet": "path to the root sheet",
   "project": "path to the project (instead of sheet)",
   "renumber": "bool, default false",
   "dryRun": "bool, default false: answer the plan and change nothing"
  },
  "output": {
   "tree": "[{name, file, id, path, page, at, sizeMm, pins: [{name, kind}], children: [...]}]",
   "problems": "[{sheet, problem: missing|unreadable|recursive}]",
   "duplicatePages": "[int]",
   "renumbered": "[{sheet, from, to}]"
  },
  "hint": "Pass the root sheet or the project. renumber writes only the numbers that change.",
  "pitfalls": [
   "A sheet file used by two sheet symbols appears twice in the tree (one instance each) but is one file."
  ],
  "related": [
   "sch_sheet_pins",
   "sch_sheet_symbol",
   "sch_create"
  ],
  "example": {
   "project": "C:/proj/Board.PrjPcb",
   "renumber": true
  },
  "longRunning": false,
  "timeoutSeconds": 30,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_sheet_pins",
  "tier": "core",
  "summary": "A sheet symbol's pins: list, add, edit (rename, kind, move along an edge) or delete. import:true adds a pin for every hierarchical port inside the child sheet that the symbol lacks; validate:true reports ports without pins, pins without ports and kind mismatches.",
  "input": {
   "sheet": "path to the parent sheet (required)",
   "sheetSymbol": "the sheet symbol's name or id (default: validate checks every one)",
   "action": "list|add|edit|delete, default list",
   "name": "string: the pin",
   "kind": "input|output|bidirectional|tri_state|passive",
   "side": "left|right|top|bottom",
   "at": "[x, y] mm: snapped to the nearest edge point",
   "newName": "string (edit)",
   "import": "bool",
   "validate": "bool",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "pins": "[{id, name, kind, side, at}]",
   "added": "[name]",
   "problems": "[{sheetSymbol, pin, problem: no_port|no_pin|kind_mismatch}]",
   "saved": "bool"
  },
  "hint": "Inputs go on the left edge and outputs on the right by default, in the first free slot. A pin joins the child's hierarchical port of the same name; wire it on the parent side at its at.",
  "pitfalls": [
   "Renaming a pin does not rename the port inside the child sheet: validate afterwards.",
   "A pin moved or deleted leaves its parent-side wire dangling."
  ],
  "related": [
   "sch_sheet_symbol",
   "sch_hierarchy",
   "sch_connect"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "sheetSymbol": "Power",
   "import": true
  },
  "longRunning": false,
  "timeoutSeconds": 30,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_reset_fields",
  "tier": "core",
  "summary": "Put parts' designator and value text (or the named fields) back where the library symbol places them, through each part's rotation and mirror. One undo step.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "references": "[\"R5\", \"C3\"]",
   "all": "bool: every part on the sheet",
   "fields": "[designator, value] by default; other field names as the tool names them",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "reset": "[{ref, field}]",
   "saved": "bool"
  },
  "hint": "Font and visibility stay as they are; only position, angle and justification move.",
  "pitfalls": [
   "The library's offsets are what the symbol's author drew; the tool's automatic field placement may put them elsewhere."
  ],
  "related": [
   "sch_edit",
   "schematic_data"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "references": [
    "R5",
    "C3"
   ]
  },
  "longRunning": true,
  "timeoutSeconds": 120,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_update_from_library",
  "tier": "native",
  "summary": "Update the placed symbols on a sheet from their libraries (all, or the listed ones) and report which changed, which already matched and which no library has.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "symbols": "[library symbol name or id, ...] (default all)",
   "library": "path to one library to take them all from (with symbols)",
   "force": "bool, default false: update even when a placed pin would be dropped",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "changed": "[{symbol, pinsAdded, pinsRemoved}]",
   "unchanged": "[symbol]",
   "notFound": "[symbol]",
   "refused": "[{symbol, droppedPins}]",
   "saved": "bool"
  },
  "hint": "Run with dryRun first. A symbol whose new version drops a placed pin is refused unless force:true. Check the sheet afterwards with run_erc.",
  "pitfalls": [
   "A pin that moved in the library moves off its wire: check with sch_pins or run_erc after an update that reports changes."
  ],
  "related": [
   "sch_swap_part",
   "schematic_data",
   "run_erc"
  ],
  "example": {
   "sheet": "C:/proj/Main.SchDoc",
   "dryRun": true
  },
  "longRunning": true,
  "timeoutSeconds": 180,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_fix_connectivity",
  "tier": "core",
  "summary": "Snap near-miss wire ends onto the pin, label, sheet pin or wire end they almost touch, within a tolerance. dryRun (the default) lists the moves; dryRun:false makes them.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "toleranceMm": "number, default 0.5",
   "dryRun": "bool, default TRUE",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "moves": "[{wireId, from, to, onto: {kind, id}, diagonal: bool}]",
   "unresolved": "[[x, y]]: dangling ends with nothing close",
   "saved": "bool"
  },
  "hint": "Only dangling wire ends move. Read the moves before applying them: diagonal:true means the snapped wire is no longer horizontal or vertical. Check with run_erc after.",
  "pitfalls": [
   "dryRun defaults to true: nothing changes until dryRun:false.",
   "A wide tolerance can snap onto the wrong pin: keep it under half the sheet's grid."
  ],
  "related": [
   "sch_trace_point",
   "run_erc"
  ],
  "example": {
   "sheet": "C:/proj/Power.SchDoc",
   "toleranceMm": 0.5,
   "dryRun": false
  },
  "longRunning": false,
  "timeoutSeconds": 60,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "render_schematic",
  "tier": "native",
  "summary": "Render a sheet to an image without opening a window, through the tool's own plotter, and keep visual baselines: baseline set stores the image, baseline compare reports the pixel drift, the changed region and a diff image.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "width": "int px, default 2000",
   "outputDir": "folder for the image (default beside the project)",
   "baseline": "set|compare",
   "threshold": "percent of pixels, default 0.5 (compare)",
   "drawingSheet": "bool, default true: include the frame and title block"
  },
  "output": {
   "png": "path",
   "width": "int",
   "height": "int",
   "driftPercent": "number (compare)",
   "pass": "bool (compare)",
   "changedRegionMm": "[x1, y1, x2, y2] (compare)",
   "diffPng": "path: the changed pixels in red (compare)",
   "rendererChanged": "bool: the tool's plotter changed since the baseline"
  },
  "hint": "A sub-sheet renders with its real designators. compare renders at the baseline's width and passes when driftPercent <= threshold. show_* verbs open a window; this one does not.",
  "pitfalls": [
   "Anti-aliasing differs between tool versions: rendererChanged:true means drift may not be a design change.",
   "A baseline is per sheet and per width; a paper size change reads as 100 percent drift."
  ],
  "related": [
   "sch_page",
   "export_pdf"
  ],
  "example": {
   "sheet": "C:/proj/Power.SchDoc",
   "baseline": "compare"
  },
  "longRunning": true,
  "timeoutSeconds": 300,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_create",
  "tier": "core",
  "summary": "Create an empty schematic sheet with a paper size and title block; optionally add it to a project as a child sheet of the root. It places no parts or nets (build_schematic does).",
  "input": {
   "sheet": "path of the sheet to create (required)",
   "paper": "A4, A3 ... USLetter or custom",
   "orientation": "portrait|landscape",
   "widthMm": "number (custom)",
   "heightMm": "number (custom)",
   "title": "string",
   "date": "string",
   "rev": "string",
   "company": "string",
   "comments": "[string]",
   "project": "path: add the sheet to this project under its root sheet",
   "sheetName": "string: the sheet symbol's name in the root",
   "at": "[x, y] mm: where the sheet symbol goes on the root",
   "dryRun": "bool, default false: answer the plan and change nothing"
  },
  "output": {
   "sheet": "path",
   "page": "int",
   "sheetSymbol": "{id, name, at} or null",
   "created": "bool"
  },
  "hint": "Without project the sheet stands alone. With project it is linked from the root sheet as a child sheet with the next page number.",
  "pitfalls": [
   "Never overwrites: an existing file is refused.",
   "A new child sheet has no pins on its symbol: add hierarchical ports inside, then sch_sheet_pins {import:true}."
  ],
  "related": [
   "sch_page",
   "sch_hierarchy",
   "sch_sheet_pins",
   "sch_place_part"
  ],
  "example": {
   "sheet": "C:/proj/Power.SchDoc",
   "project": "C:/proj/Board.PrjPcb",
   "sheetName": "Power",
   "title": "Power"
  },
  "longRunning": false,
  "timeoutSeconds": 30,
  "proposedBy": "kicad-lane",
  "since": "0.2.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "export_odb",
  "tier": "native",
  "summary": "Export the board as ODB++ (copper, drill, stack-up, netlist and parts in one archive) through the tool's own exporter.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "outputDir": "folder for the output (default beside the board)",
   "units": "mm|in, default mm",
   "compression": "zip|tgz|none, default zip"
  },
  "output": {
   "files": "[path]",
   "outputDir": "path"
  },
  "hint": "Send the archive to a fab that takes ODB++ instead of Gerbers. export_manufacturing makes the Gerber set.",
  "pitfalls": [
   "Run run_drc first: the file carries the board's errors with it."
  ],
  "related": [
   "export_manufacturing",
   "export_ipc2581",
   "run_drc"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc"
  },
  "longRunning": true,
  "timeoutSeconds": 300,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "export_ipc2581",
  "tier": "native",
  "summary": "Export the board as IPC-2581: one XML file with copper, drill, stack-up, netlist and BOM, through the tool's own exporter.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "outputDir": "folder for the output (default beside the board)",
   "version": "B|C, default C",
   "units": "mm|in, default mm",
   "compress": "bool, default false: zip the XML",
   "bomFields": "{mpn, manufacturer, distributorPn, distributor}: the part field names that carry these, so the embedded BOM is useful to the fab"
  },
  "output": {
   "file": "path"
  },
  "hint": "Name the part fields with bomFields, or the BOM inside the file carries no part numbers.",
  "pitfalls": [
   "Run run_drc first: the file carries the board's errors with it."
  ],
  "related": [
   "export_odb",
   "export_manufacturing",
   "run_drc"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "bomFields": {
    "mpn": "MPN"
   }
  },
  "longRunning": true,
  "timeoutSeconds": 300,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "export_ipc356",
  "tier": "native",
  "summary": "Export the IPC-D-356 netlist of the board, for bare-board electrical test (flying probe or bed of nails).",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "outputDir": "folder for the output (default beside the board)"
  },
  "output": {
   "file": "path"
  },
  "hint": "Send it with the Gerbers when the fab tests boards against the netlist.",
  "pitfalls": [
   "Run run_drc first: the file carries the board's errors with it."
  ],
  "related": [
   "export_manufacturing",
   "netlist"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc"
  },
  "longRunning": true,
  "timeoutSeconds": 300,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "export_gencad",
  "tier": "native",
  "summary": "Export the board as GenCAD 1.4, the input of test-fixture tools and some assembly houses' CAM.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "outputDir": "folder for the output (default beside the board)",
   "uniquePins": "bool, default false: rename duplicate pad numbers (several fixture tools need it)",
   "flipBottomPads": "bool, default false",
   "useDrillOrigin": "bool, default false: coordinates from the drill origin instead of the board's origin"
  },
  "output": {
   "file": "path"
  },
  "hint": "Ask the fixture or assembly house which options it needs; uniquePins is the common one.",
  "pitfalls": [
   "Run run_drc first: the file carries the board's errors with it."
  ],
  "related": [
   "export_manufacturing",
   "export_ipc356"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "uniquePins": true
  },
  "longRunning": true,
  "timeoutSeconds": 300,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "export_dxf",
  "tier": "native",
  "summary": "Export chosen board layers to DXF, one file per layer (the outline, panel drawings, stencils, enclosure work).",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "layers": "[\"Edge.Cuts\", \"F.Cu\"]: layer names (required; there is no sensible default)",
   "outputDir": "folder for the output (default beside the board)",
   "units": "mm|in, default mm",
   "contours": "bool, default false: join outline segments into polylines (most CAM and laser tools want it)",
   "titleBlock": "bool, default false",
   "excludeDesignators": "bool, default false",
   "excludeValues": "bool, default false",
   "useDrillOrigin": "bool, default false"
  },
  "output": {
   "files": "[{layer, path}]"
  },
  "hint": "One file per layer, named after the board and the layer. For an enclosure drawing export Edge.Cuts with contours:true.",
  "pitfalls": [
   "The board's DXF only: a mechanical DXF of a 3D design is a different job and not this verb."
  ],
  "related": [
   "render_board_layers",
   "export_step"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "layers": [
    "Edge.Cuts"
   ],
   "contours": true
  },
  "longRunning": true,
  "timeoutSeconds": 300,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "render_board_3d",
  "tier": "native",
  "summary": "Render a 3D picture of the board from one side to an image file, through the tool's own renderer, without opening a window.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "side": "top|bottom|left|right|front|back, default top",
   "width": "int px, default 1600",
   "height": "int px, default 900",
   "quality": "basic|high, default basic (high raytraces and is much slower)",
   "background": "default|transparent|opaque",
   "zoom": "number, default 1.0",
   "perspective": "bool, default false",
   "format": "png|jpg, default png",
   "outputDir": "folder for the output (default beside the board)"
  },
  "output": {
   "image": "path",
   "width": "int",
   "height": "int",
   "side": "string"
  },
  "hint": "One call per side: top and bottom for a review. A flat image of chosen layers is render_board_layers; show_3d_board opens a window instead.",
  "pitfalls": [
   "Parts without a 3D model render as bare pads: check them with bodies first."
  ],
  "related": [
   "render_board_layers",
   "render_schematic",
   "bodies",
   "show_3d_board"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "side": "top"
  },
  "longRunning": true,
  "timeoutSeconds": 600,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "estimate_cost",
  "tier": "checks",
  "summary": "The board's numbers a fab quote needs (size, layers, thickness, smallest track, gap and drill, holes, SMD and through-hole parts and joints, unique parts) and a rough price table at the quantities asked, with every assumption stated and the price source named with the date it was read.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "quantities": "[5, 10, 30, 100] (default)",
   "assembly": "bool, default false: add an assembly estimate",
   "fab": "the price list to use, default jlcpcb"
  },
  "output": {
   "board": "{sizeMm, layers, thicknessMm, minTrackMm, minGapMm, minDrillMm, holes, smdParts, thtParts, smdJoints, thtJoints, uniqueParts}",
   "prices": "[{quantity, board, assembly, total, currency}]",
   "assumptions": "[string]",
   "source": "{name, url, read: date}"
  },
  "hint": "An order of magnitude, not a quote: parts, shipping and options are left out. For a real quote send the manufacturing files to the fab.",
  "pitfalls": [
   "Prices change: source names the price list and the date it was read; an old date means an old price."
  ],
  "related": [
   "fab_check",
   "export_manufacturing",
   "bom"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "quantities": [
    5,
    50
   ]
  },
  "longRunning": false,
  "timeoutSeconds": 60,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "remove_parts",
  "tier": "core",
  "summary": "Remove placed parts from the board by designator, as one undo step. The library is not touched (that is remove_footprint).",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",
   "refs": "[\"R7\", \"R8\"] (required)",
   "allowLocked": "bool, default false",
   "dryRun": "bool, default false: answer the plan and change nothing"
  },
  "output": {
   "removed": "[{ref, nets: [string]}]",
   "failed": "[{ref, error}]",
   "revision": "string: the board's new revision"
  },
  "hint": "Each removed part lists the nets its pads carried. A locked part is refused (part_locked) unless allowLocked:true.",
  "pitfalls": [
   "Tracks and vias that met the pads stay: routing_state shows what is left dangling.",
   "A part still in the schematic comes back at the next update_pcb."
  ],
  "related": [
   "move_parts",
   "routing_state",
   "update_pcb"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "refs": [
    "TP3"
   ],
   "expectedRevision": "<rev>"
  },
  "longRunning": true,
  "timeoutSeconds": 130,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "edit_parts",
  "tier": "core",
  "summary": "Edit placed parts: value, designator, any field (add, change, remove), do-not-populate, exclusion from the BOM or position files, mounting type and the lock. One undo step.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",
   "edits": "[{ref, value?, newRef?, fields?: {name: value | null (remove)}, dnp?: bool, excludeFromBom?: bool, excludeFromPos?: bool, mount?: smd|through_hole|other, locked?: bool}] (required)",
   "dryRun": "bool, default false: answer the plan and change nothing"
  },
  "output": {
   "edited": "[{ref, before, after}]",
   "failed": "[{ref, error}]",
   "revision": "string: the board's new revision"
  },
  "hint": "Fields the tool requires (designator, value) cannot be removed. Read the parts first with component_data.",
  "pitfalls": [
   "Board-side edits of what the schematic owns are lost at the next update_pcb: change the schematic instead (sch_edit).",
   "A designator already taken is refused."
  ],
  "related": [
   "component_data",
   "part_parameters",
   "sch_edit"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "edits": [
    {
     "ref": "R7",
     "value": "4k7",
     "dnp": true
    }
   ],
   "expectedRevision": "<rev>"
  },
  "longRunning": true,
  "timeoutSeconds": 130,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "align_parts",
  "tier": "core",
  "summary": "Line parts up on a common left, right, top, bottom or centre line, or space them evenly, by courtyard box or by anchor point. One undo step, with move_parts' checks.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",
   "refs": "[\"C1\", \"C2\", \"C3\"] (required)",
   "mode": "left|right|top|bottom|centerX|centerY|distributeX|distributeY (required)",
   "by": "courtyard|anchor, default courtyard",
   "to": "mm: the line to align on (default from the group)",
   "gapMm": "number: the spacing for distribute (default even spacing between the outer two)",
   "allowOverlap": "bool, default false",
   "allowOutside": "bool, default false",
   "dryRun": "bool, default false: answer the plan and change nothing"
  },
  "output": {
   "targets": "[{ref, x, y}]",
   "mismatches": "[{ref, asked, got}]",
   "revision": "string: the board's new revision"
  },
  "hint": "Without to, left takes the group's smallest x, right the largest, top the highest edge and bottom the lowest (y up); centre lines take the mean. distribute keeps the outer two in place.",
  "pitfalls": [
   "Rotation and side are kept: align parts of the same orientation for a clean row.",
   "A courtyard collision or a part off the board is refused, as in move_parts."
  ],
  "related": [
   "move_parts",
   "placement_check"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "refs": [
    "C4",
    "C5",
    "C6"
   ],
   "mode": "top",
   "expectedRevision": "<rev>"
  },
  "longRunning": true,
  "timeoutSeconds": 130,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "set_layer_count",
  "tier": "core",
  "summary": "Set the board's copper layer count (2, 4, 6 or 8): the layer table and the stack-up, keeping the board thickness.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "count": "2|4|6|8 (required)",
   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",
   "dryRun": "bool, default false: answer the plan and change nothing"
  },
  "output": {
   "layers": "[string]: the copper layers now",
   "stackup": "the new stack-up, as layer_stack answers it",
   "revision": "string: the board's new revision"
  },
  "hint": "New inner layers are signal layers In1.Cu ... Read the result with layer_stack.",
  "pitfalls": [
   "A layer being removed that still carries copper or graphics is refused (layers_in_use, with the counts per layer).",
   "New dielectrics are generic: re-check an impedance-controlled stack-up with layer_stack.",
   "Net classes and design rules are not changed."
  ],
  "related": [
   "layer_stack",
   "copper_layers",
   "layers_in_use"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "count": 4
  },
  "longRunning": false,
  "timeoutSeconds": 60,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "remove_graphics",
  "tier": "core",
  "summary": "Remove board graphics (lines, rectangles, circles, arcs, polygons, texts, dimensions) by id, or every one on a layer and of a kind. One undo step.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",
   "ids": "[id]",
   "layer": "\"F.SilkS\": every graphic on this layer",
   "kinds": "[line|rect|circle|arc|polygon|text|dimension]",
   "dryRun": "bool, default false: answer the plan and change nothing"
  },
  "output": {
   "removed": "[{id, kind, layer, points}]",
   "revision": "string: the board's new revision"
  },
  "hint": "Board-level graphics only; graphics inside parts are footprint_primitives. An unknown id refuses the whole call (unknown_ids).",
  "pitfalls": [
   "Removing Edge.Cuts graphics removes the board outline.",
   "A layer or kind filter without ids removes every match: dry-run it first."
  ],
  "related": [
   "remove_items",
   "footprint_primitives",
   "silk_state"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "layer": "Dwgs.User",
   "dryRun": true
  },
  "longRunning": true,
  "timeoutSeconds": 130,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "import_svg",
  "tier": "core",
  "summary": "Import SVG artwork (a logo, a label) as filled polygons on a silkscreen, copper, mask or user layer, at a position and size; curves flattened, holes kept. One undo step.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",
   "svgPath": "path to the .svg",
   "svg": "the SVG text (instead of svgPath)",
   "at": "[x, y] mm (required)",
   "widthMm": "number: the artwork's width (or scale)",
   "scale": "number, default 1",
   "anchor": "topleft|center, default topleft: which point of the artwork at names",
   "layer": "default F.SilkS",
   "mirror": "bool, default true on bottom layers",
   "net": "a net for artwork on copper",
   "toleranceMm": "number, default 0.02: curve flattening",
   "dryRun": "bool, default false: answer the plan and change nothing"
  },
  "output": {
   "polygons": "int",
   "sizeMm": "[w, h]",
   "ids": "[id]",
   "skipped": "[{element, why}]",
   "revision": "string: the board's new revision"
  },
  "hint": "Filled shapes import; text and images are listed in skipped (convert text to paths first). A shape inside another becomes a hole.",
  "pitfalls": [
   "Stroke-only artwork imports nothing: give the SVG filled shapes.",
   "On copper the shapes are graphics: give net to tie them to a net, and run run_drc.",
   "On a bottom layer the artwork is mirrored so it reads correctly from the back; mirror:false keeps it as drawn."
  ],
  "related": [
   "apply_silkscreen",
   "silk_state",
   "run_drc"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "svgPath": "C:/proj/logo.svg",
   "at": [
    120,
    95
   ],
   "widthMm": 10,
   "layer": "F.SilkS",
   "expectedRevision": "<rev>"
  },
  "longRunning": true,
  "timeoutSeconds": 130,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "copy_routing",
  "tier": "core",
  "summary": "Copy the tracks and vias inside a box to an offset, remapping nets by pairing parts (a designator map or pattern), so a repeated channel gets the same routing. One undo step.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",
   "box": "[x1, y1, x2, y2] mm (required): the source",
   "offset": "[dx, dy] mm (required)",
   "refMap": "{\"U1\": \"U5\"}: pair parts, so each pad's net maps to the partner pad's net",
   "refPattern": "{from: \"CH1_*\", to: \"CH2_*\"}: pair parts by designator pattern",
   "netMap": "{\"SIG\": \"SIG2\"}: overrides",
   "keepUnmappedNets": "bool, default false",
   "layers": "[layer]: copy only these",
   "validate": "bool, default true: run the tool's DRC on the result before committing",
   "dryRun": "bool, default false: answer the plan and change nothing"
  },
  "output": {
   "copied": "{tracks: int, vias: int}",
   "netMap": "{from: to}: the pairing used",
   "skipped": "[{item, why}]",
   "drc": "{ran, newErrors}",
   "revision": "string: the board's new revision"
  },
  "hint": "A track is copied when both ends are in the box, a via when its centre is. Without a remap the copy keeps its nets. Dry-run first and check netMap.",
  "pitfalls": [
   "Only through vias are copied: blind and buried vias are skipped.",
   "The copy connects only where the target pads sit at the same offset: place the target channel identically first (replicate_layout).",
   "One source net mapping to two target nets is refused (net_map_conflict) unless netMap settles it."
  ],
  "related": [
   "replicate_layout",
   "route_net",
   "routing_state"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "box": [
    10,
    10,
    30,
    25
   ],
   "offset": [
    25,
    0
   ],
   "refPattern": {
    "from": "CH1_*",
    "to": "CH2_*"
   },
   "expectedRevision": "<rev>"
  },
  "longRunning": true,
  "timeoutSeconds": 130,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "cross_probe",
  "tier": "app",
  "summary": "From a schematic part to the board part linked to it, and back, by designator, the schematic symbol's id or its sheet path; optionally select them in the tool.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "ref": "\"U1\"",
   "symbolId": "the schematic symbol's id",
   "path": "the symbol's sheet path",
   "schematic": "path to a sheet of the project (default the project's)",
   "select": "bool, default false: also select the matches in the tool"
  },
  "output": {
   "matches": "[{board: {ref, id, side, x, y, rotation}, schematic: {sheet, id, ref, symbol, value}, linked: bool}]",
   "symbolWithoutPart": "[ref]"
  },
  "hint": "Reads the open board when the tool serves it, else the file.",
  "pitfalls": [
   "linked:false means the board part has no link to a symbol: placed by hand, or update_pcb never ran."
  ],
  "related": [
   "selection",
   "update_pcb",
   "component_data"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "ref": "U3"
  },
  "longRunning": false,
  "timeoutSeconds": 60,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "check_clearance",
  "tier": "checks",
  "summary": "Measure the gaps between parts, courtyard to courtyard or pad copper to pad copper, for the listed parts or the whole board, and report every pair under a threshold, closest first.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "refs": "[\"U1\", \"C3\"]: keep pairs that involve one of these (default every part)",
   "mode": "courtyard|pads, default courtyard",
   "thresholdMm": "number, default 0.25 (courtyard) or 0.2 (pads)",
   "includeSameNet": "bool, default false (pads)",
   "maxPairs": "int, default 200"
  },
  "output": {
   "pairs": "[{a, b, distanceMm, overlapping: bool, touching: bool}]",
   "clean": "bool",
   "thresholdMm": "number",
   "measuredOn": "courtyard outline|courtyard box|pads"
  },
  "hint": "Computed from the board model: courtyards compare only parts on the same side, pads only copper that shares a side.",
  "pitfalls": [
   "Rounded pads may be measured as their full rectangle, so a gap can read a little small: the tool's DRC (run_drc) is the authority."
  ],
  "related": [
   "placement_check",
   "run_drc",
   "align_parts"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "refs": [
    "U1"
   ],
   "mode": "pads",
   "thresholdMm": 0.2
  },
  "longRunning": false,
  "timeoutSeconds": 60,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "place_decoupling",
  "tier": "checks",
  "summary": "Plan positions for decoupling capacitors beside an IC's power pins (each cap just outside the courtyard, its power pad facing the pin), answered as move_parts arguments; dryRun:false applies them through move_parts.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "ic": "\"U1\" (required)",
   "caps": "[\"C1\", \"C2\"] (default every capacitor across ground and one of the IC's power nets)",
   "gapMm": "number, default 0.3",
   "dryRun": "bool, default TRUE",
   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed (to apply)"
  },
  "output": {
   "placements": "[{cap, pin, side, x, y, rotation, padToPinMm}]",
   "skipped": "[{cap, why: other_side|no_shared_power_net|no_free_spot}]",
   "moveArgs": "move_parts arguments",
   "validation": "move_parts' courtyard and outline check of the plan",
   "revision": "string, when applied"
  },
  "hint": "Read the plan, then apply it with dryRun:false and expectedRevision, or send moveArgs to move_parts yourself.",
  "pitfalls": [
   "Caps on the other side of the board are skipped: move them to the IC's side first (move_parts with side).",
   "It places; it does not route: route the stubs with route_net."
  ],
  "related": [
   "move_parts",
   "route_net",
   "placement_check"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "ic": "U1"
  },
  "longRunning": true,
  "timeoutSeconds": 130,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "plan_fanout",
  "tier": "checks",
  "summary": "Plan the fanout of a BGA or QFN/QFP: the pad pitch, dogbone or via-in-pad per pad, the escape layer, surface stubs for the outer ring and a via grid for an exposed pad, answered as route_net arguments, one call per net.",
  "input": {
   "filePath": "path to the board file (default: the board open in the tool)",
   "ref": "\"U3\" (required)",
   "style": "auto|dogbone|via-in-pad, default auto",
   "escapeLayer": "a layer name (default the first inner layer, else the opposite side)",
   "viaMm": "via diameter",
   "viaDrillMm": "via drill",
   "widthMm": "track width",
   "clearanceMm": "number, default 0.1",
   "pitchMm": "override the detected pitch",
   "stubMm": "number, default 0.4",
   "surfaceOuterRing": "bool, default true"
  },
  "output": {
   "package": "bga|perimeter",
   "pitchMm": "number",
   "style": "string",
   "pads": "[{pad, net, action: surface|dogbone|via-in-pad|stub+via|thermal-via-grid|skip}]",
   "calls": "[route_net arguments]",
   "minViaToPadMm": "number"
  },
  "hint": "auto picks dogbone when a via fits between four pads with the clearance, else via-in-pad. Send each call to route_net with filePath and expectedRevision, dry run first.",
  "pitfalls": [
   "Via-in-pad needs filled and capped vias (IPC-4761 type VII): tell the user before committing it.",
   "The plan does not check stubs against other parts' copper; route_net checks each call before it commits."
  ],
  "related": [
   "route_net",
   "place_vias",
   "fab_check"
  ],
  "example": {
   "filePath": "C:/proj/Board.PcbDoc",
   "ref": "U3"
  },
  "longRunning": false,
  "timeoutSeconds": 60,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "project_create",
  "tier": "core",
  "summary": "Create a new project folder with a project file, an empty schematic and an empty board (2 to 32 copper layers), with a title and text variables.",
  "input": {
   "parentDir": "folder to create the project in (required)",
   "name": "string (required): the project and folder name",
   "title": "string",
   "layers": "int, default 2",
   "fabRules": "a fab name from adom/pcb-design-rules, recorded to apply once the board has content",
   "textVariables": "{\"REV\": \"A\"}",
   "dryRun": "bool, default false: answer the plan and change nothing"
  },
  "output": {
   "project": "path",
   "files": "[path]"
  },
  "hint": "Next: draw the outline (set_outline), then place and route. fabRules is recorded, not applied.",
  "pitfalls": [
   "A folder that already holds a project is refused.",
   "The board has no outline yet: set it before routing or exporting."
  ],
  "related": [
   "project_info",
   "sch_create",
   "set_outline"
  ],
  "example": {
   "parentDir": "C:/Users/me/Documents/Projects",
   "name": "widget",
   "layers": 4
  },
  "longRunning": false,
  "timeoutSeconds": 30,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "project_info",
  "tier": "core",
  "summary": "A project at a glance: name, files with sizes and dates, the sheet tree, the board (layers, parts, nets, size), text variables, net classes, last change, and whether the tool has it open. Read only.",
  "input": {
   "project": "path to the project file, its folder or any of its documents (required)"
  },
  "output": {
   "name": "string",
   "files": "[{path, bytes, modified}]",
   "sheets": "the sheet tree, as sch_hierarchy answers it",
   "board": "{layers, parts, nets, sizeMm}",
   "textVariables": "{name: value}",
   "netClasses": "[string]",
   "modified": "date",
   "open": "bool: the tool has a document of this project open"
  },
  "hint": "Read this before renaming, snapshotting or editing a project.",
  "pitfalls": [],
  "related": [
   "sch_hierarchy",
   "board_summary",
   "open_project"
  ],
  "example": {
   "project": "C:/proj/Board.PrjPcb"
  },
  "longRunning": false,
  "timeoutSeconds": 30,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "project_rename",
  "tier": "core",
  "summary": "Rename a project: the project file, the root sheet, the board and the tool's side files, with the references inside them updated. Refused while the tool has the project open.",
  "input": {
   "project": "path to the project file (required)",
   "newName": "string (required)",
   "dryRun": "bool, default false: answer the plan and change nothing"
  },
  "output": {
   "renamed": "[{from, to}]",
   "changed": "[{file, what}]"
  },
  "hint": "Dry-run first: the plan lists every file renamed and what changes inside each. Close the project in the tool first.",
  "pitfalls": [
   "Child sheet files keep their names; only the documents named after the project are renamed.",
   "The folder keeps its name.",
   "Take a project_snapshot first if the project is not under version control."
  ],
  "related": [
   "project_snapshot",
   "project_info",
   "close"
  ],
  "example": {
   "project": "C:/proj/Old.PrjPcb",
   "newName": "widget-v2",
   "dryRun": true
  },
  "longRunning": false,
  "timeoutSeconds": 60,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "project_snapshot",
  "tier": "native",
  "summary": "A dated copy of the project's documents into <project>/snapshots/<stamp>[-label]/, with PDFs of the schematic and the board made by the tool.",
  "input": {
   "project": "path to the project file (required)",
   "label": "string: added to the folder name",
   "pdfs": "bool, default true"
  },
  "output": {
   "folder": "path",
   "files": "[path]",
   "pdfs": "{made: [path], skipped: why}"
  },
  "hint": "Take one before a risky edit (a rename, a big re-route). Libraries in sub-folders are referenced, not copied.",
  "pitfalls": [
   "A snapshot of an open project holds what is saved on disk, not unsaved edits: save first."
  ],
  "related": [
   "project_rename",
   "export_pdf",
   "save"
  ],
  "example": {
   "project": "C:/proj/Board.PrjPcb",
   "label": "before-routing"
  },
  "longRunning": true,
  "timeoutSeconds": 300,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "read_footprint",
  "tier": "core",
  "summary": "Every detail of one library footprint: pads (number, type, shape, position, size, drill, layers), the layers it uses, its courtyard box, graphics per layer, attributes, properties and 3D models. The library mirror of read_symbol; footprint_primitives reads a part placed on the board.",
  "input": {
   "libraryPath": "path to the footprint library",
   "name": "the footprint's name (with libraryPath)",
   "libId": "\"Lib:Name\": resolved through the project's and then the global library table",
   "project": "path to the project, for libId"
  },
  "output": {
   "name": "string",
   "pads": "[{number, type, shape, at, sizeMm, drillMm, layers, rotation}]",
   "layers": "[string]",
   "courtyardMm": "[x1, y1, x2, y2]",
   "graphics": "{layer: count}",
   "attributes": "{mount, excludeFromBom, excludeFromPos, dnp}",
   "properties": "{name: value}",
   "models": "[{path, offset, scale, rotate}]"
  },
  "hint": "Read before edit_footprint, and to check pin 1 and the pad numbers against the symbol.",
  "pitfalls": [],
  "related": [
   "edit_footprint",
   "read_symbol",
   "footprint_primitives",
   "list_library"
  ],
  "example": {
   "libId": "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm"
  },
  "longRunning": false,
  "timeoutSeconds": 60,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "edit_footprint",
  "tier": "core",
  "summary": "Edit a library footprint in place: change, delete, add or renumber pads; add, replace or delete graphics on a layer; set its description, tags and attributes; replace, add or delete 3D models. Everything not edited stays as it was.",
  "input": {
   "libraryPath": "path to the footprint library (required)",
   "name": "the footprint's name (required)",
   "pads": "[{number, set?: {sizeMm, at, shape, drillMm, layers, rotation, type, newNumber}, delete?: true}]",
   "addPads": "[pad]",
   "renumber": "{map: {\"1\": \"A1\"}} | {sequential: true, start?: 1}",
   "graphics": "[{layer, mode: append|replace|delete, widthMm?, shapes: [{type: line|arc|rect|circle|poly, ...}]}]",
   "metadata": "{description?, tags?, attributes?: {mount, excludeFromBom, excludeFromPos, dnp}}",
   "models": "{mode: replace|append|delete, list: [{path, offset, scale, rotate}]}",
   "dryRun": "bool, default false: answer the plan and change nothing"
  },
  "output": {
   "changes": "[string]: what was done, in order"
  },
  "hint": "Operations run in the order pads, addPads, renumber, graphics, metadata, models. An edited pad keeps its id.",
  "pitfalls": [
   "Boards that already use the footprint keep their own copy: update them with swap_footprint.",
   "Graphics replace and delete touch shapes only, never text on that layer."
  ],
  "related": [
   "read_footprint",
   "create_footprint",
   "swap_footprint",
   "add_body"
  ],
  "example": {
   "libraryPath": "C:/lib/Mine.PcbLib",
   "name": "SOT-23_Mine",
   "pads": [
    {
     "number": "1",
     "set": {
      "sizeMm": [
       1.0,
       0.8
      ]
     }
    }
   ]
  },
  "longRunning": false,
  "timeoutSeconds": 30,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "export_library_part",
  "tier": "native",
  "summary": "Export one library part into its own small library files: a symbol library with only its symbol, a footprint library with only its footprint, and its 3D model file.",
  "input": {
   "part": "the part's symbol name or library id (required)",
   "footprint": "a footprint name (default the symbol's own)",
   "what": "[symbol, footprint, model] (default all three)",
   "outputDir": "folder for the files"
  },
  "output": {
   "exports": "{symbol: path, footprint: path, model: path}",
   "missing": "[what]"
  },
  "hint": "Use it to hand one part to another project or another tool.",
  "pitfalls": [
   "success is false when any piece asked for is missing; exports still carries what was written."
  ],
  "related": [
   "read_symbol",
   "read_footprint",
   "import_part"
  ],
  "example": {
   "part": "IN-S42ATA"
  },
  "longRunning": true,
  "timeoutSeconds": 130,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "create_part_project",
  "tier": "native",
  "summary": "Generate a small real project (schematic and board) around one library part, so the part can be shown and tested in every view: schematic, 2D board and 3D board.",
  "input": {
   "part": "the part's symbol name or library id (required)",
   "footprint": "a footprint name (default the symbol's own)",
   "projectName": "string (default from the part)",
   "outputDir": "folder (default the user's projects folder)",
   "overwrite": "bool, default false: replace a project of that name"
  },
  "output": {
   "project": "path",
   "schematic": "path",
   "board": "path"
  },
  "hint": "The board keeps the footprint's 3D model, so render_board_3d and show_3d_board show the real part. One part by design.",
  "pitfalls": [
   "The part's symbol and footprint must both be in a library the tool can find.",
   "An existing project of that name is refused unless overwrite:true."
  ],
  "related": [
   "export_library_part",
   "render_board_3d",
   "show_3d_board",
   "import_part"
  ],
  "example": {
   "part": "IN-S42ATR"
  },
  "longRunning": true,
  "timeoutSeconds": 130,
  "proposedBy": "kicad-lane",
  "since": "0.3.0",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "simulate",
  "tier": "app",
  "summary": "Run a circuit simulation of the design's schematic and return the signals as data: an operating point, a DC sweep, an AC sweep or a transient, with the nets and source currents asked for.",
  "input": {
   "schematic": "the design or sheet to simulate (the bridge's own path or id) (required)",
   "analysis": "{type: op} | {type: dc, source, start, stop, step} | {type: ac, sweep: dec|oct|lin, points, start, stop} (Hz) | {type: tran, step, stop, start?} (s) | {type: noise, source, output, reference?, sweep: dec|oct|lin, points, start, stop} (Hz: the output and input-referred noise of output against reference, driven from source) | {type: raw, text: \".ac dec 20 10 1meg\"} (a bridge that cannot run raw SPICE refuses it with not_supported); default the analysis the design carries",
   "probes": "[{net: \"OUT\"} | {current: \"V1\"}]; default every net (a bridge may cap the count)",
   "sweep": "{parameter, start, stop, step, scale?: \"lin\" | \"dec\" | \"oct\"}: optional; steps a part's value (\"R4\") or a model parameter (\"Q1.BF\"), one run per value; for lin, step is the increment, for dec and oct the points per decade or octave; a bridge may cap the number of runs",
   "temperatures": "{start, stop, step} (°C): optional; one run per temperature",
   "monteCarlo": "{runs, distribution?: \"uniform\" | \"gaussian\", seed?, tolerances: {resistor?, capacitor?, inductor?, transistor?, dcSource?, digital?} (%)}: optional; the analysis runs again with every part drawn within its kind's tolerance, each run its own signal; the same seed draws the same values",
   "points": "int, default 200: a ceiling on the points returned per signal; decimation keeps the first and last points and every extremum (the run itself is not coarsened)"
  },
  "output": {
   "signals": "[{signal: \"V(OUT)\", x: [..], y: [..], xUnit: s|Hz|V, yUnit: V|A|dB, phase?: [..] (AC, degrees, unwrapped)}]; an op gives one point per signal; with sweep or temperatures each run is its own signal, with step saying which run it is (\"R4 = 300\", \"T = 85\"), so a reader groups runs by signal + step; a Monte Carlo run's step lists the values drawn (\"R3 = 9038.1, C6 = 1.0004e-10\"), so any run can be reproduced; a noise analysis answers onoise and inoise (yUnit V/rtHz) over frequency",
   "totals": "noise analysis: {onoise, inoise}, the integrated output and input-referred noise in V",
   "missing": "[probe]: probes the run did not have",
   "notSimulated": "[ref]: parts the run left out for want of a simulation model, when the sheet is only partly modelled, so a reader knows the result covers only part of the circuit (empty when every part was simulated)",
   "available": "[signal name]",
   "engine": "the simulator and its version, e.g. \"ngspice 46 (KiCad 10.0.7)\""
  },
  "hint": "AC signals are the magnitude in dB with phase in degrees beside it. Every part needs a simulation model: passives work from their values, sources come from the tool's simulation library, ICs need a model file.",
  "pitfalls": [
   "simulation_failed carries the simulator's own message: a part without a model, a node with no DC path to ground, or a bad analysis.",
   "points thins the reply, not the run: a long transient with a tiny step still takes its time.",
   "A partly modelled sheet still runs and names the parts it left out in notSimulated; a sheet with no modelled parts refuses with no_model.",
   "A bridge that cannot sweep refuses sweep or temperatures with not_supported; it never runs once and returns a single trace as if it were the sweep (ngspice has no .step: loop with alter per value).",
   "A bridge that cannot run a noise analysis or a Monte Carlo (or draw one of its tolerance kinds) refuses with not_supported; it never answers something else in its place."
  ],
  "related": [
   "export_spice",
   "run_erc",
   "sch_place_part"
  ],
  "example": {
   "schematic": "C:/proj/filter.kicad_sch",
   "analysis": {
    "type": "ac",
    "sweep": "dec",
    "points": 20,
    "start": 10,
    "stop": 1000000
   },
   "probes": [
    {
     "net": "OUT"
    }
   ]
  },
  "proposedBy": "kicad-lane",
  "since": "0.14.0",
  "agreedBy": [
   "standard-lane",
   "altium-lane",
   "fusion-lane"
  ]
 },
 {
  "name": "export_spice",
  "tier": "app",
  "summary": "Write the design's SPICE netlist with the tool's own exporter, and say what it holds.",
  "input": {
   "schematic": "the design or sheet (required)",
   "outputPath": "path for the netlist (default beside the design)"
  },
  "output": {
   "path": "the netlist file",
   "dialect": "ngspice | pspice | ltspice | xspice",
   "elements": "int: parts in the netlist",
   "analyses": "[the analysis lines the design carries]",
   "includes": "[the model files it includes]"
  },
  "hint": "A part without a simulation model is left out or becomes a comment: give it one before simulating.",
  "pitfalls": [
   "Model files are included by the path the part's model field gives: keep them where every machine finds them."
  ],
  "related": [
   "simulate"
  ],
  "example": {
   "schematic": "C:/proj/filter.kicad_sch"
  },
  "proposedBy": "kicad-lane",
  "since": "0.14.0",
  "agreedBy": [
   "standard-lane",
   "altium-lane",
   "fusion-lane"
  ]
 },
 {
  "name": "verb_times",
  "tier": "app",
  "summary": "Measured run times of this bridge's verbs on this machine: per verb the count, p50, p90, max, last and failures, from its own run log, slowest p90 first.",
  "input": {
   "limit": "int, default 40: how many verbs"
  },
  "output": {
   "verbs": "[{verb, count, p50Sec, p90Sec, maxSec, lastSec, failures}]",
   "since": "when the log starts"
  },
  "hint": "p90 is the headline: a p50 of 15 s next to a p90 of 400 s is two code paths under one name. failures counts runs that returned success:false; a verb that fails fast is a different bug from a slow one.",
  "pitfalls": [
   "Times are this machine's: a slower box or a bigger board moves them."
  ],
  "related": [
   "prewarm"
  ],
  "example": {
   "limit": 20
  },
  "proposedBy": "kicad-lane",
  "since": "0.25.1",
  "agreedBy": [
   "standard-lane",
   "fusion-lane"
  ]
 },
 {
  "name": "prewarm",
  "tier": "app",
  "summary": "Get this machine ready for a fast first call: detect the tool, seed its first-run settings, dismiss first-run wizards and repair what the first real call would otherwise do slowly. Idempotent.",
  "input": {},
  "output": {
   "steps": "[{step, done, skipped?, why?}]",
   "ready": "bool"
  },
  "hint": "The bridge host may run it once after an install or update; running it again changes nothing. Everything it does is what the first real verb would otherwise do in the user's face.",
  "pitfalls": [
   "It never opens a document or takes the foreground."
  ],
  "related": [
   "verb_times"
  ],
  "example": {},
  "proposedBy": "kicad-lane",
  "since": "0.25.1",
  "agreedBy": [
   "standard-lane",
   "fusion-lane"
  ]
 },
 {
  "name": "render_board",
  "tier": "native",
  "summary": "A rendered 3D picture (PNG or JPG) of a board from one side, made by the tool's own renderer with no window: optionally framed on parts, turned for an isometric view, raytraced.",
  "input": {
   "filePath": "the board (required)",
   "side": "top | bottom | left | right | front | back, default top",
   "width": "px, default 1600",
   "height": "px, default 900",
   "quality": "basic | high (raytraced)",
   "background": "default | transparent | opaque",
   "zoom": "float",
   "perspective": "bool",
   "format": "png | jpg",
   "refs": "[ref]: frame these parts (camera on their pads' centre, zoomed to them)",
   "marginMm": "mm round framed parts, default 2",
   "rotate": "'x,y,z' degrees, e.g. '-45,0,45' for isometric",
   "outputDir": "folder for the image"
  },
  "output": {
   "path": "the image",
   "framed": "{refs, pivot, zoom} when refs was given"
  },
  "hint": "One call per side (top and bottom for a review). refs frames parts for a close look; quality high raytraces and takes longer.",
  "pitfalls": [
   "The picture is of the saved board file: unsaved edits are not in it."
  ],
  "related": [
   "zoom_to",
   "library_views",
   "render_schematic"
  ],
  "example": {
   "filePath": "C:/proj/board.kicad_pcb",
   "side": "top",
   "refs": [
    "J1"
   ],
   "rotate": "-45,0,45"
  },
  "proposedBy": "kicad-lane",
  "since": "0.25.1",
  "agreedBy": [
   "standard-lane",
   "fusion-lane"
  ]
 },
 {
  "name": "export_pos",
  "tier": "native",
  "summary": "Export the pick-and-place (component position, CPL) file of a board, optionally in a fab's assembly format (JLCPCB's columns).",
  "input": {
   "filePath": "the board (required)",
   "side": "both | front | back, default both",
   "format": "csv | ascii | gerber, default csv",
   "units": "mm | in, default mm",
   "smdOnly": "bool",
   "excludeDnp": "bool, default true",
   "fab": "jlcpcb: also write the fab's own CPL columns",
   "outputDir": "folder"
  },
  "output": {
   "files": "[path]",
   "parts": "int per side"
  },
  "hint": "Pair it with a BOM and Gerbers for an assembly order; export_manufacturing writes all three in one call.",
  "pitfalls": [
   "Rotations follow the tool's convention; a fab may need its own offsets per package.",
   "A format the tool cannot write (Altium's pick-and-place generator has no Gerber form) is answered unsupported with the reason."
  ],
  "related": [
   "export_manufacturing",
   "bom",
   "assembly_check"
  ],
  "example": {
   "filePath": "C:/proj/board.kicad_pcb",
   "fab": "jlcpcb"
  },
  "proposedBy": "kicad-lane",
  "since": "0.25.1",
  "agreedBy": [
   "standard-lane",
   "altium-lane",
   "fusion-lane"
  ]
 },
 {
  "name": "sch_batch",
  "tier": "core",
  "summary": "Apply a list of schematic edits to one sheet in one read and one write, all or nothing: each op is a standard schematic verb with its own arguments, seeing the sheet as the earlier ops left it.",
  "input": {
   "filePath": "the sheet (required)",
   "ops": "[{op: a standard schematic verb's name (sch_place_part, sch_connect_pins, sch_connect, sch_edit, sch_edit_label, sch_junction, sch_bus, sch_bus_entry, sch_text, sch_delete_wire, sch_split_wire, sch_move_region, sch_reset_fields, sch_update_from_library, annotate, ...), ...that verb's arguments}] (required)",
   "dryRun": "bool: report the plan, write nothing"
  },
  "output": {
   "results": "[{op, output, uuid?}] in order",
   "ercBefore": "the sheet's ERC counts before",
   "ercAfter": "and after",
   "failedOp": "the index of the op that failed (nothing is written then)",
   "mutated": "bool"
  },
  "hint": "A part placed in op 0 can be wired in op 1. A failing op aborts the whole batch: failedOp names it and the sheet is unchanged.",
  "pitfalls": [
   "A bridge whose tool cannot undo a partial batch answers partial: it says which ops ran before the failure."
  ],
  "related": [
   "build_schematic",
   "sch_place_part",
   "sch_connect_pins",
   "run_erc"
  ],
  "example": {
   "filePath": "C:/proj/board.kicad_sch",
   "ops": [
    {
     "op": "sch_place_part",
     "libId": "Device:R",
     "reference": "R9",
     "at": [
      100,
      80
     ]
    },
    {
     "op": "sch_connect_pins",
     "pairs": [
      [
       "R9.1",
       "U1.3"
      ]
     ]
    }
   ]
  },
  "proposedBy": "kicad-lane",
  "since": "0.26.4",
  "agreedBy": [
   "standard-lane",
   "fusion-lane"
  ]
 },
 {
  "name": "log_tail",
  "tier": "app",
  "summary": "What the tool said about itself since an offset: its own log lines and alerts (warnings and errors), so a verb that looks successful while the tool complains is caught.",
  "input": {
   "sinceOffset": "int, default 0: where the last call stopped (its next)",
   "maxBytes": "int, default 200000",
   "errorsOnly": "bool: only errors and warnings"
  },
  "output": {
   "entries": "[{level, text}] newest last",
   "next": "the offset to pass as sinceOffset next time",
   "truncated": "bool"
  },
  "hint": "Carry next from call to call to see only what is new. Read it after a verb that succeeded but left the tool looking unhappy.",
  "pitfalls": [
   "A tool that writes no log of its own answers what the bridge captured from the instances it launched."
  ],
  "related": [
   "dialog_log",
   "state",
   "diagnostics"
  ],
  "example": {
   "sinceOffset": 0,
   "errorsOnly": true
  },
  "proposedBy": "kicad-lane",
  "since": "0.26.4",
  "agreedBy": [
   "standard-lane",
   "fusion-lane"
  ]
 },
 {
  "name": "sch_no_connect",
  "tier": "core",
  "summary": "Put a no-connect marker on a sheet, at a point or on a pin, or remove one by its sch_items id. One undo step.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "at": "[x, y] mm: a point",
   "points": "[[x, y]] mm: several points",
   "pin": "designator.pin, e.g. U1.12",
   "pins": "[designator.pin]",
   "id": "a marker's id from sch_items (with remove)",
   "remove": "bool, default false: remove the marker at id or at",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "added": "[{id, at}]",
   "removed": "[id]",
   "failed": "[{item, error}]",
   "saved": "bool"
  },
  "hint": "Use it for a pin left open on purpose, so the ERC stops reporting it. sch_items {kinds:[noConnects]} lists the markers with their ids.",
  "pitfalls": [
   "A bridge whose tool has no such marker answers not_supported, with the reason (Fusion's schematic has none)."
  ],
  "related": [
   "sch_items",
   "sch_connect",
   "run_erc"
  ],
  "example": {
   "sheet": "C:/proj/board.kicad_sch",
   "pin": "U1.12"
  },
  "proposedBy": "kicad-lane",
  "since": "0.31.1",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "sch_label",
  "tier": "core",
  "summary": "Put a net label on an existing wire at a point, or delete one. sch_connect labels a pin through a new stub, and sch_edit_label changes labels that already exist.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "text": "the net name (required to add)",
   "at": "[x, y] mm: a point on the wire",
   "kind": "local|global|hierarchical, default local",
   "rotation": "0|90|180|270, default 0",
   "remove": "bool, default false: delete the label named by id, or by text with at",
   "id": "a label's id from sch_items (with remove)",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "label": "{id, text, kind, at, rotation} when added",
   "removed": "[id]",
   "saved": "bool"
  },
  "hint": "The label names the net of the wire it touches: check with sch_trace_point at the same point, or netlist.",
  "pitfalls": [
   "A label placed where no wire runs connects nothing, and is reported by the ERC, not by this verb."
  ],
  "related": [
   "sch_connect",
   "sch_edit_label",
   "sch_items",
   "sch_trace_point"
  ],
  "example": {
   "sheet": "C:/proj/board.kicad_sch",
   "text": "VIN",
   "at": [
    63.5,
    54.61
   ]
  },
  "proposedBy": "kicad-lane",
  "since": "0.31.1",
  "agreedBy": [
   "altium-lane",
   "fusion-lane"
  ]
 },
 {
  "name": "sch_wire",
  "tier": "core",
  "summary": "Draw a wire through given points on a sheet, in the same units as the other sch_* wiring verbs. One undo step.",
  "input": {
   "sheet": "path to the schematic sheet file (required)",
   "points": "[[x, y], ...] mm, two or more (required)",
   "junctions": "bool, default true: add a junction where the wire ends on another wire",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "save": "bool, default true: save the sheet after the edit"
  },
  "output": {
   "wires": "[{id, from, to}] one per segment",
   "junctionsAdded": "[{id, at}]",
   "saved": "bool"
  },
  "hint": "For wiring between points that aren't pins, such as a bus of stubs or a route around a part. sch_connect_pins draws between two pins and works out the path.",
  "pitfalls": [
   "Points that are not on the sheet's grid may not reach a pin: read the pin's position first with sch_pins."
  ],
  "related": [
   "sch_connect_pins",
   "sch_split_wire",
   "sch_delete_wire",
   "sch_items"
  ],
  "example": {
   "sheet": "C:/proj/board.kicad_sch",
   "points": [
    [
     50.8,
     54.61
    ],
    [
     76.2,
     54.61
    ]
   ]
  },
  "proposedBy": "kicad-lane",
  "since": "0.31.1",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "place_parts",
  "tier": "core",
  "summary": "Put footprints from a library onto the current board, each with its position, rotation and side, and read them back. One undo step.",
  "input": {
   "filePath": "the board (default the current one)",
   "parts": "[{library, footprint, ref?, value?, x, y, rotation?: 0, side?: top|bottom, nets?: {pad: net}}] mm and degrees (required)",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "expectedRevision": "optional: refused with stale_board if the board changed"
  },
  "output": {
   "results": "[ok|err:...] per part",
   "placed": "[{ref, x, y, rotation, side}]",
   "revision": "string"
  },
  "hint": "For parts with no sheet behind them: mounting hardware, test points, or a board built without a schematic. A taken designator is refused and the next free one is named.",
  "pitfalls": [
   "On a board with a schematic, parts normally arrive through update_pcb: a part placed here is on no sheet, and the next update_pcb lists it in removeParts.",
   "Fusion's linked board is partial: only a standalone board takes a direct add."
  ],
  "related": [
   "update_pcb",
   "move_parts",
   "remove_parts",
   "routing_state"
  ],
  "example": {
   "parts": [
    {
     "library": "Resistor_SMD",
     "footprint": "R_0603_1608Metric",
     "ref": "R12",
     "x": 120.0,
     "y": 95.0
    }
   ]
  },
  "proposedBy": "kicad-lane",
  "since": "0.31.1",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "edit_tracks",
  "tier": "native",
  "summary": "Change given tracks by the handle routing_state returns: width, layer and ends. One undo step, read back.",
  "input": {
   "filePath": "the board (default the current one)",
   "tracks": "[{id, width?, layer?, start?: [x, y], end?: [x, y]}] mm; id is the track's handle from routing_state (required)",
   "dryRun": "bool, default false: answer the plan and change nothing",
   "expectedRevision": "optional: refused with stale_board if the board changed"
  },
  "output": {
   "results": "[ok|err:...] per track",
   "changes": "[{id, before, after}]",
   "verified": "bool: every change read back",
   "revision": "string"
  },
  "hint": "set_track_width works by net or class; this works on the tracks you name, for one neck or one layer swap. A track that moves off its pad is refused or shows in routing_drc, depending on the bridge.",
  "pitfalls": [
   "Changing a track's layer does not add the vias its ends now need: check with routing_drc."
  ],
  "related": [
   "routing_state",
   "set_track_width",
   "remove_items",
   "routing_drc"
  ],
  "example": {
   "tracks": [
    {
     "id": "<handle>",
     "width": 0.5
    }
   ]
  },
  "proposedBy": "kicad-lane",
  "since": "0.31.1",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "model_check",
  "tier": "checks",
  "summary": "Per part: is there a 3D model, where is it, is the file found, and does it hold geometry. For a library footprint or a whole board. Read only.",
  "input": {
   "filePath": "a board: every part on it",
   "library": "a footprint library (with footprint)",
   "footprint": "one footprint's name",
   "limit": "int, default 50: parts reported on a board"
  },
  "output": {
   "parts": "[{name, models: [{path, location: embedded|file|cloud, found: bool, hasGeometry: bool}], issues: [string]}]",
   "checked": "int",
   "ok": "bool: every part has a model that is found and holds geometry"
  },
  "hint": "Run it before a 3D export or a fab handoff. Whether the body sits in the right place stays with bodies: this verb only says the model is there and usable.",
  "pitfalls": [
   "A bridge whose models live in the cloud reports found as whether the reference resolves."
  ],
  "related": [
   "bodies",
   "lint_library",
   "export_3d"
  ],
  "example": {
   "filePath": "C:/proj/board.kicad_pcb"
  },
  "proposedBy": "kicad-lane",
  "since": "0.31.1",
  "agreedBy": [
   "altium-lane"
  ]
 },
 {
  "name": "extensions",
  "tier": "app",
  "summary": "The tool's own plugins and add-ons: list what is installed, install one, remove one. Not install_extension, which is the bridge's own helper inside the tool.",
  "input": {
   "action": "list|install|remove, default list",
   "id": "the package's identifier (install, remove)",
   "source": "a repository URL or a local package file (install)",
   "version": "optional (install)",
   "checkUpdates": "bool, default true (list)"
  },
  "output": {
   "extensions": "[{id, name, version, kind, updateAvailable?, latestVersion?}]",
   "count": "int",
   "installed": "{id, version} after install",
   "removed": "id after remove"
  },
  "hint": "Read the list before installing, and restart the tool if the reply says the plugin loads at startup.",
  "pitfalls": [
   "Altium and Fusion list, and refuse install and remove by name: their pages can't be driven."
  ],
  "related": [
   "install_extension",
   "extension_ping",
   "state"
  ],
  "example": {
   "action": "list"
  },
  "proposedBy": "kicad-lane",
  "since": "0.31.1",
  "agreedBy": [
   "altium-lane"
  ]
 }
]