component
ECE1200-I
Public Made by Adomby adom
Microchip Tech Interface - Specialized, QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
Publish 0.1.0
e7475d8
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{
"slug": "ece1200-i",
"version": "0.1.0",
"type": "component",
"description": "Microchip Tech Interface - Specialized, QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"communication interface chip",
"ece1200-i",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"ece1200-i.kicad_sym",
"ece1200-i.kicad_mod",
"ece1200-i.glb",
"ece1200-i.step",
"ece1200-i.lbr",
"docs/hero.png",
"docs/ece1200-i-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"ece1200-i-hero.glb",
"ece1200-i-hero.overlay.json",
"ece1200-i-etched.glb"
],
"component": {
"mpn": "ECE1200-I",
"manufacturer": "Microchip Tech",
"package": "QFN-40-EP(5x5)",
"pin_count": 41,
"category": "Communication Interface Chip",
"subcategory": "Interface - Specialized",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/29c621813fbc066a47da66b6e3d13849.pdf",
"parts": {
"symbol": "ece1200-i.kicad_sym",
"footprint": "ece1200-i.kicad_mod",
"model_3d": "ece1200-i-hero.glb",
"model_3d_plain": "ece1200-i-etched.glb",
"model_3d_step": "ece1200-i-etched.step",
"model_3d_step_plain": "ece1200-i.step",
"lbr": "ece1200-i.lbr"
},
"distributor_links": {
"lcsc": "C633264"
},
"distributor_check": {
"checked_at": "2026-11-09T06:33:22Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "ESPI_ALERT#",
"type": "output",
"description": "eSPI Alert output, low-active, in the VTR_18 power well; used when the Host enables it for multi-slave systems."
},
{
"number": "2",
"name": "VTR_18",
"type": "power_in",
"description": "1.8V I/O power supply for the eSPI pins (1.71V to 1.89V operating, -0.3V to +1.98V absolute max)."
},
{
"number": "3",
"name": "ESPI_IO2",
"type": "bidirectional",
"description": "eSPI data bus bit 2, used only in x4 mode, in the VTR_18 power well."
},
{
"number": "4",
"name": "ESPI_IO0",
"type": "bidirectional",
"description": "eSPI data bus bit 0 (MOSI in x1 mode; LS data bit in wider modes), in the VTR_18 power well."
},
{
"number": "5",
"name": "ESPI_CLK",
"type": "input",
"description": "eSPI clock input in the VTR_18 power well, supporting up to 50 MHz operation."
},
{
"number": "6",
"name": "ESPI_IO1",
"type": "bidirectional",
"description": "eSPI data bus bit 1 (MISO in x1 mode); by default also presents ALERT# state while the bus is idle with a single slave."
},
{
"number": "7",
"name": "ESPI_IO3",
"type": "bidirectional",
"description": "eSPI data bus bit 3 (MS bit), used only in x4 mode, in the VTR_18 power well."
},
{
"number": "8",
"name": "VTR_18",
"type": "power_in",
"description": "1.8V I/O power supply for the eSPI pins (1.71V to 1.89V operating, -0.3V to +1.98V absolute max)."
},
{
"number": "9",
"name": "TEST",
"type": "input",
"description": "Test enable input that must be kept permanently low in normal operation; when high it redefines all pin functions."
},
{
"number": "10",
"name": "LPC_EN",
"type": "input",
"description": "Senses the Runtime (VCC) power plane, intended to come from PCH_PWROK, enabling VCC-emulated pins."
},
{
"number": "11",
"name": "VTR_33",
"type": "power_in",
"description": "3.3V I/O power supply for 3.3V pins (3.135V to 3.465V operating, -0.3V to +3.63V absolute max)."
},
{
"number": "12",
"name": "BOOT_DONE",
"type": "input",
"description": "Selects eSPI slave role: high for Primary, low for Secondary, and low-then-high delays assuming the Primary role; also selects the function of pin 35."
},
{
"number": "13",
"name": "PLTRST#",
"type": "input",
"description": "Platform reset input from the Chipset (CPU/PCI reset), 3.3V DIO type."
},
{
"number": "14",
"name": "VTR_CORE_18",
"type": "power_in",
"description": "1.8V internal logic core power supply (1.71V to 1.89V operating, -0.3V to +1.98V absolute max)."
},
{
"number": "15",
"name": "SUSCLK",
"type": "input",
"description": "Suspend clock input (32 kHz) used for oscillator frequency lock, backdrive tolerant (-0.5V to +3.63V while powered off)."
},
{
"number": "16",
"name": "SUS_STAT#",
"type": "output",
"description": "Suspend status output driven from the SUS_STAT# Virtual Wire, PCI type in the VTR_33 well."
},
{
"number": "17",
"name": "SUSACK#",
"type": "input",
"description": "Suspend acknowledge input whose edges are transmitted to the PCH as the SUS_ACK# Virtual Wire; should follow SUSWARN#, and is ignored when BOOT_DONE is low."
},
{
"number": "18",
"name": "RESETI#",
"type": "input",
"description": "Power-on reset input, low-active, driven from RSMRST#; resets all registers and logic to defaults."
},
{
"number": "19",
"name": "SUSWARN#",
"type": "output",
"description": "Presents the state of the SUS_WARN# Virtual Wire; also the XNOR chain test output."
},
{
"number": "20",
"name": "ESPI_STRAP_0",
"type": "input",
"description": "Should remain open (N/C) except for test purposes; input to the XNOR Chain test mode."
},
{
"number": "21",
"name": "ESPI_STRAP_1",
"type": "input",
"description": "Should remain open (N/C) except for test purposes; input to the XNOR Chain test mode."
},
{
"number": "22",
"name": "VTR_33",
"type": "power_in",
"description": "3.3V I/O power supply for 3.3V pins (3.135V to 3.465V operating, -0.3V to +3.63V absolute max)."
},
{
"number": "23",
"name": "LPC_CLK0",
"type": "output",
"description": "LPC clock output, nominal 24 MHz, enabled only when LPC_EN is high; VOH min 2.4V at -16mA, VOL max 0.4V at 16mA."
},
{
"number": "24",
"name": "LPC_CLK1",
"type": "output",
"description": "LPC clock output, nominal 24 MHz, enabled only when LPC_EN is high; VOH min 2.4V at -16mA, VOL max 0.4V at 16mA."
},
{
"number": "25",
"name": "LAD0",
"type": "bidirectional",
"description": "LPC multiplexed address/data bit 0 (PCI type); also test mode selection code bit in XNOR chain."
},
{
"number": "26",
"name": "LAD1",
"type": "bidirectional",
"description": "LPC multiplexed address/data bit 1 (PCI type); also test mode selection code bit in XNOR chain."
},
{
"number": "27",
"name": "LAD2",
"type": "bidirectional",
"description": "LPC multiplexed address/data bit 2 (PCI type); also test mode selection code bit in XNOR chain."
},
{
"number": "28",
"name": "LAD3",
"type": "bidirectional",
"description": "LPC multiplexed address/data bit 3 (PCI type); part of the XNOR chain."
},
{
"number": "29",
"name": "LFRAME#",
"type": "output",
"description": "LPC frame output from the LPC master, PCI type in the VTR_33 well."
},
{
"number": "30",
"name": "VTR_33",
"type": "power_in",
"description": "3.3V I/O power supply for 3.3V pins (3.135V to 3.465V operating, -0.3V to +3.63V absolute max)."
},
{
"number": "31",
"name": "SER_IRQ",
"type": "bidirectional",
"description": "Serial IRQ interface pin supporting Continuous and Quiet modes, PCI type."
},
{
"number": "32",
"name": "CLKRUN#",
"type": "bidirectional",
"description": "LPC clock run control interface (PCI_24 type) used to gate LPC clocks."
},
{
"number": "33",
"name": "No Connect",
"type": "unconnected",
"description": "No connect."
},
{
"number": "34",
"name": "No Connect",
"type": "unconnected",
"description": "No connect."
},
{
"number": "35",
"name": "SUSPWRDNACK / HOST_RST_ACK",
"type": "output",
"description": "Outputs SUSPWRDNACK when BOOT_DONE=1 (Primary) or HOST_RST_ACK when BOOT_DONE=0 (Secondary)."
},
{
"number": "36",
"name": "ESPI_RESET#",
"type": "input",
"description": "eSPI power-on and global reset input from the Host, low-active, in the VTR_18 well."
},
{
"number": "37",
"name": "No Connect",
"type": "unconnected",
"description": "No connect."
},
{
"number": "38",
"name": "No Connect",
"type": "unconnected",
"description": "No connect."
},
{
"number": "39",
"name": "No Connect",
"type": "unconnected",
"description": "No connect."
},
{
"number": "40",
"name": "ESPI_CS#",
"type": "input",
"description": "eSPI chip select input, low-active, in the VTR_18 power well."
},
{
"number": "41",
"name": "VSS",
"type": "power_in",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-sonnet-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Datasheet ordering code is ECE1200-I/LD (40-VQFN LDX, 5x5 mm, 2.7x2.7 mm exposed pad); only one pack; ESPI_CLK is named ESPI_CLK in the pin table but eSPI_CLOCK in Table 5-2; SUSCLK 32 kHz frequency is ; Section 7.4.3.1 mentions a VREF_CPU pin that does not exist in the pinout table.",
"4/41 pins cited to the wrong page (name found elsewhere): ['12:BOOT_DONE@p26', '17:SUSACK#@p25', '18:RESETI#@p34', '19:SUSWARN#@p25']"
],
"pages_sent": 38,
"cost_usd": 0.1998,
"at": "2026-11-09T06:33:12"
},
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/29c621813fbc066a47da66b6e3d13849.pdf",
"pages": 86,
"sha256": "5e6c87a1bdf84529",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 41,
"described": 41,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ece1200-i.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
5.0,
5.0,
0.77
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "8f37bc7a9aab4742c34f137d9822c0352acc227532830034555744338483cdfc",
"checked": "2026-11-09",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ece1200-i-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
5.0,
5.0,
0.77
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "51fa5d3e8225f2ecaa15d101441d5de73fab92ccf7807f29c5150e4f0412d756",
"checked": "2026-11-09",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}