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Microchip Tech Interface - Specialized, QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ECE1200-I

Microchip Tech · Interface - Specialized · QFN-40-EP(5x5)

ECE1200-I from Microchip Tech, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ESPI_ALERT#	output	eSPI Alert output, low-active, in the VTR_18 power well; used when the Host enables it for multi-slave systems.
2	VTR_18	power_in	1.8V I/O power supply for the eSPI pins (1.71V to 1.89V operating, -0.3V to +1.98V absolute max).
3	ESPI_IO2	bidirectional	eSPI data bus bit 2, used only in x4 mode, in the VTR_18 power well.
4	ESPI_IO0	bidirectional	eSPI data bus bit 0 (MOSI in x1 mode; LS data bit in wider modes), in the VTR_18 power well.
5	ESPI_CLK	input	eSPI clock input in the VTR_18 power well, supporting up to 50 MHz operation.
6	ESPI_IO1	bidirectional	eSPI data bus bit 1 (MISO in x1 mode); by default also presents ALERT# state while the bus is idle with a single slave.
7	ESPI_IO3	bidirectional	eSPI data bus bit 3 (MS bit), used only in x4 mode, in the VTR_18 power well.
8	VTR_18	power_in	1.8V I/O power supply for the eSPI pins (1.71V to 1.89V operating, -0.3V to +1.98V absolute max).
9	TEST	input	Test enable input that must be kept permanently low in normal operation; when high it redefines all pin functions.
10	LPC_EN	input	Senses the Runtime (VCC) power plane, intended to come from PCH_PWROK, enabling VCC-emulated pins.
11	VTR_33	power_in	3.3V I/O power supply for 3.3V pins (3.135V to 3.465V operating, -0.3V to +3.63V absolute max).
12	BOOT_DONE	input	Selects eSPI slave role: high for Primary, low for Secondary, and low-then-high delays assuming the Primary role; also selects the function of pin 35.
13	PLTRST#	input	Platform reset input from the Chipset (CPU/PCI reset), 3.3V DIO type.
14	VTR_CORE_18	power_in	1.8V internal logic core power supply (1.71V to 1.89V operating, -0.3V to +1.98V absolute max).
15	SUSCLK	input	Suspend clock input (32 kHz) used for oscillator frequency lock, backdrive tolerant (-0.5V to +3.63V while powered off).
16	SUS_STAT#	output	Suspend status output driven from the SUS_STAT# Virtual Wire, PCI type in the VTR_33 well.
17	SUSACK#	input	Suspend acknowledge input whose edges are transmitted to the PCH as the SUS_ACK# Virtual Wire; should follow SUSWARN#, and is ignored when BOOT_DONE is low.
18	RESETI#	input	Power-on reset input, low-active, driven from RSMRST#; resets all registers and logic to defaults.
19	SUSWARN#	output	Presents the state of the SUS_WARN# Virtual Wire; also the XNOR chain test output.
20	ESPI_STRAP_0	input	Should remain open (N/C) except for test purposes; input to the XNOR Chain test mode.
21	ESPI_STRAP_1	input	Should remain open (N/C) except for test purposes; input to the XNOR Chain test mode.
22	VTR_33	power_in	3.3V I/O power supply for 3.3V pins (3.135V to 3.465V operating, -0.3V to +3.63V absolute max).
23	LPC_CLK0	output	LPC clock output, nominal 24 MHz, enabled only when LPC_EN is high; VOH min 2.4V at -16mA, VOL max 0.4V at 16mA.
24	LPC_CLK1	output	LPC clock output, nominal 24 MHz, enabled only when LPC_EN is high; VOH min 2.4V at -16mA, VOL max 0.4V at 16mA.
25	LAD0	bidirectional	LPC multiplexed address/data bit 0 (PCI type); also test mode selection code bit in XNOR chain.
26	LAD1	bidirectional	LPC multiplexed address/data bit 1 (PCI type); also test mode selection code bit in XNOR chain.
27	LAD2	bidirectional	LPC multiplexed address/data bit 2 (PCI type); also test mode selection code bit in XNOR chain.
28	LAD3	bidirectional	LPC multiplexed address/data bit 3 (PCI type); part of the XNOR chain.
29	LFRAME#	output	LPC frame output from the LPC master, PCI type in the VTR_33 well.
30	VTR_33	power_in	3.3V I/O power supply for 3.3V pins (3.135V to 3.465V operating, -0.3V to +3.63V absolute max).
31	SER_IRQ	bidirectional	Serial IRQ interface pin supporting Continuous and Quiet modes, PCI type.
32	CLKRUN#	bidirectional	LPC clock run control interface (PCI_24 type) used to gate LPC clocks.
33	No Connect	unconnected	No connect.
34	No Connect	unconnected	No connect.
35	SUSPWRDNACK / HOST_RST_ACK	output	Outputs SUSPWRDNACK when BOOT_DONE=1 (Primary) or HOST_RST_ACK when BOOT_DONE=0 (Secondary).
36	ESPI_RESET#	input	eSPI power-on and global reset input from the Host, low-active, in the VTR_18 well.
37	No Connect	unconnected	No connect.
38	No Connect	unconnected	No connect.
39	No Connect	unconnected	No connect.
40	ESPI_CS#	input	eSPI chip select input, low-active, in the VTR_18 power well.
41	VSS	power_in	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-40-EP(5x5)
Category	Communication Interface Chip
Pins	41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
1.8V Core Logic Power Supply	VTR_CORE_18	1.71	1.8	1.89	V	with respect to ground	60
1.8V I/O Power Supply	VTR_18	1.71	1.8	1.89	V	with respect to ground	60
3.3V I/O Power Supply	VTR_33	3.135	3.3	3.465	V	with respect to ground	60
1.8V Logic Power Supply absolute	VTR_CORE_18	-0.3		1.98	V	with respect to ground	59
1.8V I/O Power Supply absolute	VTR_18	-0.3		1.98	V	with respect to ground	59
3.3V I/O Power Supply absolute	VTR_33	-0.3		3.63	V	with respect to ground	59
Storage Temperature Range		-55		150	oC		59
Operating Temperature Range (Industrial)		-40		85	oC	Industrial	59
Operating Ambient Temperature Range - Industrial	TA	-40		85	°C		61
Operating Junction Temperature Range - Industrial	TJ			125	°C		61
Input Low Voltage (PCI)	Vil	-0.5			V		60
Input Leakage Current (PCI)	Iil	-10		10	uA	Vin > 0V and Vin < VTR_33	60
Input Pin Capacitance (PCI)	Cin			10	pF		60
Output High Voltage (LCLK)	VOH	2.4			V	IOH = -16mA	60
Output Low Voltage (LCLK)	VOL			0.4	V	IOL = 16mA	60
Input High Voltage (DIO)	VIHI	2			V		61
Input Low Voltage (DIO)	VILI			0.8	V		61
Input Leakage Current (DIO)	IIH	-10		10	uA		61
Output High Voltage (DIO)	VOH	2.4			V	IOH = -8mA	61
Output Low Voltage (DIO)	VOL			0.4	V	IOL = 8mA	61
Input Pin Capacitance (DIO)	CIN			20	pF		61
Input Leakage (SUSCLK backdrive)	IIL	-2		12.3	uA	TA = 0oC to +85oC; VIN=3.47V, and all VTR=0V	61
Clock to Valid (PCI pin type)	t1	2		11	ns	PCI pin type	66
Clock to Valid (PCI_24 pin type)	t1	3		15	ns	PCI_24 pin type	66
Clock to Actively Driven (PCI pin type)	t2	2		11	ns	PCI pin type	66
Clock to Actively Driven (PCI_24 pin type)	t2	3		15	ns	PCI_24 pin type	66
Clock to Floating (PCI, PCI_24)	t3			28	ns	PCI, PCI_24 pin types	66
Valid Input Setup to Clock	t1	7			ns		67
Valid Input Hold From Clock	t2	0			ns		67
Wake from Deep Sleep	tW			3	ms	Wake from deep sleep by eSPI access	68
Schmitt Hysteresis (DIO)	VHYS		400		mV		61
Package Thermal Resistance junction-to-ambient, 40-pin VQFN	JA		50		°C/W	airflow 0 m/s	62
Package Thermal Resistance junction-to-case, 40-pin VQFN	JC		9.4		°C/W		62
Package Thermal Resistance junction-to-board, 40-pin VQFN	JB		31		°C/W		62
Supply current VTR_33			11.45		mA	Case 1: Full On, Active LPC Traffic, with both LPC Clocks Running	62
Supply current VTR_18			25		uA	Case 1: Full On, Active LPC Traffic, with both LPC Clocks Running	62
Supply current VTR_CORE_18			1.25		mA	Case 1: Full On, Active LPC Traffic, with both LPC Clocks Running	62
Supply current VTR_33			2		uA	Case 3: LPC Idle, Clocks Off	62
Supply current VTR_18			2.3		uA	Case 3: LPC Idle, Clocks Off	62
Supply current VTR_CORE_18			0.9		mA	Case 3: LPC Idle, Clocks Off	62
Supply current VTR_33			11.1		mA	Case 4: LPC On and Reset, both LPC Clocks Running (forced)	62
Supply current VTR_18			2.2		uA	Case 4: LPC On and Reset, both LPC Clocks Running (forced)	62
Supply current VTR_CORE_18			1.06		mA	Case 4: LPC On and Reset, both LPC Clocks Running (forced)	62
Supply current VTR_CORE_18			0.44		mA	Case 5: Light Sleep, LPC Clocks off and Gated Clock mode	62
Supply current VTR_CORE_18			3.6		uA	Case 6: Deep Sleep, Host C10 / S0ix, Disabled Internal Oscillator	62
Supply current VTR_33			0		uA	Case 7: LPC Unpowered, Sub-S0, LPC_EN low, eSPI Active	63
Supply current VTR_18			2.3		uA	Case 7: LPC Unpowered, Sub-S0, LPC_EN low, eSPI Active	63
Supply current VTR_CORE_18			1		mA	Case 7: LPC Unpowered, Sub-S0, LPC_EN low, eSPI Active	63
Supply current VTR_CORE_18			3.2		mA	Case 8: LPC Unpowered, eSPI Reset, eSPI_RESET# low and RESETI# high	63
Supply current VTR_18			0		uA	Case 9: Full Chip Reset, RESETI# low	63
Supply current VTR_CORE_18			2.7		uA	Case 9: Full Chip Reset, RESETI# low	63

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	PC		- Host-Programmable Base Address • Supports LPC-based SIO and EC devices such	1

CAD (KiCad official)

Symbol: ECE1200-I
Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
3D model files: ece1200-i-etched.step / ece1200-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ece1200-i.step / ece1200-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (86 pp, sha256 5e6c87a1bdf84529, retrieved 2026-11-09, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# ECE1200-I

**Microchip Tech** · Interface - Specialized · QFN-40-EP(5x5)

ECE1200-I from Microchip Tech, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ESPI_ALERT# | output | eSPI Alert output, low-active, in the VTR_18 power well; used when the Host enables it for multi-slave systems. |
| 2 | VTR_18 | power_in | 1.8V I/O power supply for the eSPI pins (1.71V to 1.89V operating, -0.3V to +1.98V absolute max). |
| 3 | ESPI_IO2 | bidirectional | eSPI data bus bit 2, used only in x4 mode, in the VTR_18 power well. |
| 4 | ESPI_IO0 | bidirectional | eSPI data bus bit 0 (MOSI in x1 mode; LS data bit in wider modes), in the VTR_18 power well. |
| 5 | ESPI_CLK | input | eSPI clock input in the VTR_18 power well, supporting up to 50 MHz operation. |
| 6 | ESPI_IO1 | bidirectional | eSPI data bus bit 1 (MISO in x1 mode); by default also presents ALERT# state while the bus is idle with a single slave. |
| 7 | ESPI_IO3 | bidirectional | eSPI data bus bit 3 (MS bit), used only in x4 mode, in the VTR_18 power well. |
| 8 | VTR_18 | power_in | 1.8V I/O power supply for the eSPI pins (1.71V to 1.89V operating, -0.3V to +1.98V absolute max). |
| 9 | TEST | input | Test enable input that must be kept permanently low in normal operation; when high it redefines all pin functions. |
| 10 | LPC_EN | input | Senses the Runtime (VCC) power plane, intended to come from PCH_PWROK, enabling VCC-emulated pins. |
| 11 | VTR_33 | power_in | 3.3V I/O power supply for 3.3V pins (3.135V to 3.465V operating, -0.3V to +3.63V absolute max). |
| 12 | BOOT_DONE | input | Selects eSPI slave role: high for Primary, low for Secondary, and low-then-high delays assuming the Primary role; also selects the function of pin 35. |
| 13 | PLTRST# | input | Platform reset input from the Chipset (CPU/PCI reset), 3.3V DIO type. |
| 14 | VTR_CORE_18 | power_in | 1.8V internal logic core power supply (1.71V to 1.89V operating, -0.3V to +1.98V absolute max). |
| 15 | SUSCLK | input | Suspend clock input (32 kHz) used for oscillator frequency lock, backdrive tolerant (-0.5V to +3.63V while powered off). |
| 16 | SUS_STAT# | output | Suspend status output driven from the SUS_STAT# Virtual Wire, PCI type in the VTR_33 well. |
| 17 | SUSACK# | input | Suspend acknowledge input whose edges are transmitted to the PCH as the SUS_ACK# Virtual Wire; should follow SUSWARN#, and is ignored when BOOT_DONE is low. |
| 18 | RESETI# | input | Power-on reset input, low-active, driven from RSMRST#; resets all registers and logic to defaults. |
| 19 | SUSWARN# | output | Presents the state of the SUS_WARN# Virtual Wire; also the XNOR chain test output. |
| 20 | ESPI_STRAP_0 | input | Should remain open (N/C) except for test purposes; input to the XNOR Chain test mode. |
| 21 | ESPI_STRAP_1 | input | Should remain open (N/C) except for test purposes; input to the XNOR Chain test mode. |
| 22 | VTR_33 | power_in | 3.3V I/O power supply for 3.3V pins (3.135V to 3.465V operating, -0.3V to +3.63V absolute max). |
| 23 | LPC_CLK0 | output | LPC clock output, nominal 24 MHz, enabled only when LPC_EN is high; VOH min 2.4V at -16mA, VOL max 0.4V at 16mA. |
| 24 | LPC_CLK1 | output | LPC clock output, nominal 24 MHz, enabled only when LPC_EN is high; VOH min 2.4V at -16mA, VOL max 0.4V at 16mA. |
| 25 | LAD0 | bidirectional | LPC multiplexed address/data bit 0 (PCI type); also test mode selection code bit in XNOR chain. |
| 26 | LAD1 | bidirectional | LPC multiplexed address/data bit 1 (PCI type); also test mode selection code bit in XNOR chain. |
| 27 | LAD2 | bidirectional | LPC multiplexed address/data bit 2 (PCI type); also test mode selection code bit in XNOR chain. |
| 28 | LAD3 | bidirectional | LPC multiplexed address/data bit 3 (PCI type); part of the XNOR chain. |
| 29 | LFRAME# | output | LPC frame output from the LPC master, PCI type in the VTR_33 well. |
| 30 | VTR_33 | power_in | 3.3V I/O power supply for 3.3V pins (3.135V to 3.465V operating, -0.3V to +3.63V absolute max). |
| 31 | SER_IRQ | bidirectional | Serial IRQ interface pin supporting Continuous and Quiet modes, PCI type. |
| 32 | CLKRUN# | bidirectional | LPC clock run control interface (PCI_24 type) used to gate LPC clocks. |
| 33 | No Connect | unconnected | No connect. |
| 34 | No Connect | unconnected | No connect. |
| 35 | SUSPWRDNACK / HOST_RST_ACK | output | Outputs SUSPWRDNACK when BOOT_DONE=1 (Primary) or HOST_RST_ACK when BOOT_DONE=0 (Secondary). |
| 36 | ESPI_RESET# | input | eSPI power-on and global reset input from the Host, low-active, in the VTR_18 well. |
| 37 | No Connect | unconnected | No connect. |
| 38 | No Connect | unconnected | No connect. |
| 39 | No Connect | unconnected | No connect. |
| 40 | ESPI_CS# | input | eSPI chip select input, low-active, in the VTR_18 power well. |
| 41 | VSS | power_in | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-40-EP(5x5) |
| Category | Communication Interface Chip |
| Pins | 41 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 1.8V Core Logic Power Supply | VTR_CORE_18 | 1.71 | 1.8 | 1.89 | V | with respect to ground | 60 |
| 1.8V I/O Power Supply | VTR_18 | 1.71 | 1.8 | 1.89 | V | with respect to ground | 60 |
| 3.3V I/O Power Supply | VTR_33 | 3.135 | 3.3 | 3.465 | V | with respect to ground | 60 |
| 1.8V Logic Power Supply absolute | VTR_CORE_18 | -0.3 |  | 1.98 | V | with respect to ground | 59 |
| 1.8V I/O Power Supply absolute | VTR_18 | -0.3 |  | 1.98 | V | with respect to ground | 59 |
| 3.3V I/O Power Supply absolute | VTR_33 | -0.3 |  | 3.63 | V | with respect to ground | 59 |
| Storage Temperature Range |  | -55 |  | 150 | oC |  | 59 |
| Operating Temperature Range (Industrial) |  | -40 |  | 85 | oC | Industrial | 59 |
| Operating Ambient Temperature Range - Industrial | TA | -40 |  | 85 | °C |  | 61 |
| Operating Junction Temperature Range - Industrial | TJ |  |  | 125 | °C |  | 61 |
| Input Low Voltage (PCI) | Vil | -0.5 |  |  | V |  | 60 |
| Input Leakage Current (PCI) | Iil | -10 |  | 10 | uA | Vin > 0V and Vin < VTR_33 | 60 |
| Input Pin Capacitance (PCI) | Cin |  |  | 10 | pF |  | 60 |
| Output High Voltage (LCLK) | VOH | 2.4 |  |  | V | IOH = -16mA | 60 |
| Output Low Voltage (LCLK) | VOL |  |  | 0.4 | V | IOL = 16mA | 60 |
| Input High Voltage (DIO) | VIHI | 2 |  |  | V |  | 61 |
| Input Low Voltage (DIO) | VILI |  |  | 0.8 | V |  | 61 |
| Input Leakage Current (DIO) | IIH | -10 |  | 10 | uA |  | 61 |
| Output High Voltage (DIO) | VOH | 2.4 |  |  | V | IOH = -8mA | 61 |
| Output Low Voltage (DIO) | VOL |  |  | 0.4 | V | IOL = 8mA | 61 |
| Input Pin Capacitance (DIO) | CIN |  |  | 20 | pF |  | 61 |
| Input Leakage (SUSCLK backdrive) | IIL | -2 |  | 12.3 | uA | TA = 0oC to +85oC; VIN=3.47V, and all VTR=0V | 61 |
| Clock to Valid (PCI pin type) | t1 | 2 |  | 11 | ns | PCI pin type | 66 |
| Clock to Valid (PCI_24 pin type) | t1 | 3 |  | 15 | ns | PCI_24 pin type | 66 |
| Clock to Actively Driven (PCI pin type) | t2 | 2 |  | 11 | ns | PCI pin type | 66 |
| Clock to Actively Driven (PCI_24 pin type) | t2 | 3 |  | 15 | ns | PCI_24 pin type | 66 |
| Clock to Floating (PCI, PCI_24) | t3 |  |  | 28 | ns | PCI, PCI_24 pin types | 66 |
| Valid Input Setup to Clock | t1 | 7 |  |  | ns |  | 67 |
| Valid Input Hold From Clock | t2 | 0 |  |  | ns |  | 67 |
| Wake from Deep Sleep | tW |  |  | 3 | ms | Wake from deep sleep by eSPI access | 68 |
| Schmitt Hysteresis (DIO) | VHYS |  | 400 |  | mV |  | 61 |
| Package Thermal Resistance junction-to-ambient, 40-pin VQFN | JA |  | 50 |  | °C/W | airflow 0 m/s | 62 |
| Package Thermal Resistance junction-to-case, 40-pin VQFN | JC |  | 9.4 |  | °C/W |  | 62 |
| Package Thermal Resistance junction-to-board, 40-pin VQFN | JB |  | 31 |  | °C/W |  | 62 |
| Supply current VTR_33 |  |  | 11.45 |  | mA | Case 1: Full On, Active LPC Traffic, with both LPC Clocks Running | 62 |
| Supply current VTR_18 |  |  | 25 |  | uA | Case 1: Full On, Active LPC Traffic, with both LPC Clocks Running | 62 |
| Supply current VTR_CORE_18 |  |  | 1.25 |  | mA | Case 1: Full On, Active LPC Traffic, with both LPC Clocks Running | 62 |
| Supply current VTR_33 |  |  | 2 |  | uA | Case 3: LPC Idle, Clocks Off | 62 |
| Supply current VTR_18 |  |  | 2.3 |  | uA | Case 3: LPC Idle, Clocks Off | 62 |
| Supply current VTR_CORE_18 |  |  | 0.9 |  | mA | Case 3: LPC Idle, Clocks Off | 62 |
| Supply current VTR_33 |  |  | 11.1 |  | mA | Case 4: LPC On and Reset, both LPC Clocks Running (forced) | 62 |
| Supply current VTR_18 |  |  | 2.2 |  | uA | Case 4: LPC On and Reset, both LPC Clocks Running (forced) | 62 |
| Supply current VTR_CORE_18 |  |  | 1.06 |  | mA | Case 4: LPC On and Reset, both LPC Clocks Running (forced) | 62 |
| Supply current VTR_CORE_18 |  |  | 0.44 |  | mA | Case 5: Light Sleep, LPC Clocks off and Gated Clock mode | 62 |
| Supply current VTR_CORE_18 |  |  | 3.6 |  | uA | Case 6: Deep Sleep, Host C10 / S0ix, Disabled Internal Oscillator | 62 |
| Supply current VTR_33 |  |  | 0 |  | uA | Case 7: LPC Unpowered, Sub-S0, LPC_EN low, eSPI Active | 63 |
| Supply current VTR_18 |  |  | 2.3 |  | uA | Case 7: LPC Unpowered, Sub-S0, LPC_EN low, eSPI Active | 63 |
| Supply current VTR_CORE_18 |  |  | 1 |  | mA | Case 7: LPC Unpowered, Sub-S0, LPC_EN low, eSPI Active | 63 |
| Supply current VTR_CORE_18 |  |  | 3.2 |  | mA | Case 8: LPC Unpowered, eSPI Reset, eSPI_RESET# low and RESETI# high | 63 |
| Supply current VTR_18 |  |  | 0 |  | uA | Case 9: Full Chip Reset, RESETI# low | 63 |
| Supply current VTR_CORE_18 |  |  | 2.7 |  | uA | Case 9: Full Chip Reset, RESETI# low | 63 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC |  | - Host-Programmable Base Address • Supports LPC-based SIO and EC devices such | 1 |

## CAD (KiCad official)

- Symbol: `ECE1200-I`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm`
- 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `ece1200-i-etched.step` / `ece1200-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ece1200-i.step` / `ece1200-i.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/ece1200-i-datasheet.pdf) (86 pp, sha256 `5e6c87a1bdf84529`, retrieved 2026-11-09, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ece1200-i-datasheet.pdf)

ECE1200-I

Verified ECE1200-I

Verification log 1 record

ECE1200-I

Pinout

Key specifications

Electrical characteristics

Materials and finish

CAD (KiCad official)

Provenance