component
EA8961SCR
Public Made by Adomby adom
Everanalog IC design DC-DC Converters, TSSOP-14L-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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EA8961SCR
Everanalog IC design · DC-DC Converters · TSSOP-14L-EP
EA8961SCR from Everanalog IC design, in a TSSOP-14L-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog ground; the EP must be connected to AGND for heat dissipation. |
| 2 | PGND | power_in | Power ground; the input bypass capacitor must be placed directly across VIN and PGND (pins 3 and 2) close to the IC. |
| 3 | VIN | power_in | Power input with a 5V to 100V input voltage range; absolute maximum -0.3V to +100V. |
| 4 | EN/UVLO | input | Dual-level enable and UVLO input: below 0.35V is shutdown, 0.35V to 1.24V is standby, and above 1.24V allows switching once VCC exceeds 3.85V; absolute maximum -0.3V to +100V. |
| 5 | RON | input | On-time setting pin; a resistor connected from this pin to VIN sets the on-time and switching frequency; absolute maximum -0.3V to +100V. |
| 6 | SS | passive | Soft-start time setting pin; an external capacitor is charged by a 10µA source from 0V to 2V, and a minimum 1nF capacitor must be used; absolute maximum -0.3V to +7V. |
| 7 | NC | unconnected | Not connected. |
| 8 | FPWM | input | Mode select pin: connect to AGND for DCM at light load and to VCC for CCM; FPWM high input voltage is 3V minimum and low input voltage is 1V maximum; absolute maximum -0.3V to +7V. |
| 9 | FB | input | Feedback voltage input with a 2V reference (1.96V to 2.04V); absolute maximum -0.3V to +7V. |
| 10 | VCC | power_out | Internal high-voltage LDO output with 4.5V to 5.5V nominal range (5.0V typical), powering internal circuitry and charging the BST capacitor; absolute maximum -0.3V to +7V. |
| 11 | BST | power_in | Power input of the internal high-side N-MOSFET gate driver; BST to SW absolute maximum is +7V and BST to VCC absolute maximum is 100V. |
| 12 | SW | output | Switching output node; absolute maximum -1.5V to +100V, with -3V allowed for 20ns. |
| 13 | SW | output | Switching output node, bonded together with pin 12; absolute maximum -1.5V to +100V, with -3V allowed for 20ns. |
| 14 | NC | unconnected | Not connected. |
| 15 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Everanalog IC design |
| Package | TSSOP-14L-EP |
| Category | Power Management (PMIC) |
| Pins | 15 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC Voltage | VCC | 4.5 | 5 | 5.5 | V | ICC = 20mA | 4 |
| VCC Current | ICC | 30 | mA | 4 | |||
| Shutdown Supply Current | ISD | 35 | 60 | uA | VEN = 0V | 4 | |
| Quiescent Current | IQ | 1.3 | 2 | mA | VFB = 3V, ILOAD = 0A | 4 | |
| Low Side MOSFET Souring Current Limit | ISOURCE-LM | 1.3 | 1.6 | 1.9 | A | 4 | |
| FB Pin Voltage Accuracy | VREF | 1.96 | 2 | 2.04 | V | 5 | |
| EN/UVLO Pin UVLO Voltage Threshold | VEN-TH | 1.2 | 1.24 | 1.27 | V | EN/UVLO Rising | 5 |
| EN/UVLO Pin Shutdown Mode Voltage Threshold | VEN-SD | 0.29 | 0.35 | V | EN/UVLO Falling | 5 | |
| EN/UVLO Pin Input Current | IEN | 15 | 20 | 25 | μA | EN/UVLO = 1.4V | 5 |
| UVLO Threshold | VUVLO | 3.85 | V | VCC Rising | 4 | ||
| UVLO Hysteresis | VUV-HYS | 200 | mV | 4 | |||
| VIN-VCC Dropout Voltage | 600 | mV | VIN = 5V, ICC = 20mA | 4 | |||
| High Side MOSFET On-Resistance | RDS(ON)-HM | 300 | mΩ | ISW = 0.5A | 4 | ||
| Low Side MOSFET On-Resistance | RDS(ON)-LM | 150 | mΩ | ISW = 0.5A | 4 | ||
| BST Pin UVLO Threshold | 2.9 | V | 4 | ||||
| BST Pin UVLO Hysteresis | 200 | mV | 4 | ||||
| High Side MOSFET Current Limit | ILIM-HM | 1.61 | A | 4 | |||
| Low Side MOSFET Sinking Current Limit | ISINK-LM | 3 | A | 4 | |||
| High Side MOSFET Current Limit Response Time | tLIM-HM | 100 | ns | ILIM-HM threshold detect to MOSFET turn off | 4 | ||
| High Side MOSFET Current Limit Turn off Time | tOFF | 16.5 | μs | FB = 0V, VIN = 72V | 4 | ||
| High Side MOSFET Current Limit Turn off Time | tOFF1 | 13 | μs | FB = 0.1V, VIN = 72V | 4 | ||
| High Side MOSFET Current Limit Turn off Time | tOFF2 | 2.7 | μs | FB = 1V, VIN = 72V | 4 | ||
| FPWM Pin Input High Voltage | VFPWM-H | 3 | V | 4 | |||
| FPWM Pin Input Low Voltage | VFPWM-L | 1 | V | 5 | |||
| Zero Current Detection | IZX | 22.5 | mA | FPWM = 0V | 5 | ||
| FB Pin Input Current | IFB | 100 | nA | 5 | |||
| Soft-Start Current | ISS | 10 | μA | SS = 0.5V | 5 | ||
| EN/UVLO Pin Shutdown Mode Voltage Hysteresis | VEN-SD-TH | 50 | mV | 5 | |||
| Thermal Shutdown Threshold | TOTP | 175 | °C | 5 | |||
| Thermal Shutdown Hysteresis | THYS | 20 | °C | 5 | |||
| Input Voltage (VIN) | VIN | -0.3 | 100 | V | 3 | ||
| EN/UVLO Pin Input Voltage | VEN | -0.3 | 100 | V | 3 | ||
| RON Pin Voltage | VRON | -0.3 | 100 | V | 3 | ||
| BST Pin Voltage | VBST | -0.3 | 107 | V | 3 | ||
| VCC Pin Voltage | VCC | -0.3 | 7 | V | 3 | ||
| FPWM Pin Voltage | VFPWM | -0.3 | 7 | V | 3 | ||
| SS Pin Voltage | VSS | -0.3 | 7 | V | 3 | ||
| FB Pin Voltage | VFB | -0.3 | 7 | V | 3 | ||
| SW Pin Voltage | VSW | -1.5 | 100 | V | 3 | ||
| BST Pin to SW Pin Voltage | -0.3 | 7 | V | 3 | |||
| BST Pin to VCC Pin Voltage | 100 | V | 3 | ||||
| SW Pin to AGND Pin Voltage | -3 | V | 20ns | 3 | |||
| Ambient Temperature operating Range | TA | -40 | 85 | °C | 3 | ||
| Maximum Junction Temperature | TJmax | 150 | °C | 3 | |||
| Lead Temperature (Soldering) | 260 | °C | 10 sec | 3 | |||
| Storage Temperature Range | TS | -65 | 150 | °C | 3 | ||
| Minimum Soft-Start Capacitor | CSS | 1 | nF | In all applications | 10 | ||
| Minimum On-Time of RON | tON_min | 150 | ns | RON at maximum VIN | 11 | ||
| TSSOP14L-EP Power Dissipation (PDmax) | PDmax | 3.2 | W | TA=25°C | 3 | ||
| TSSOP14L-EP Thermal Resistance (θJC) | θJC | 23.7 | °C/W | 3 | |||
| TSSOP14L-EP Thermal Resistance (θJA) | θJA | 39.5 | °C/W | 3 |
CAD (KiCad official)
- Symbol:
EA8961SCR - Footprint:
Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm - 3D model: TSSOP-14L-EP (KiCad packages3D, STEP)
- 3D model files:
ea8961scr-etched.step/ea8961scr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ea8961scr.step/ea8961scr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Everanalog IC design datasheet (19 pp, sha256
da8e008f8e473fd1, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# EA8961SCR
**Everanalog IC design** · DC-DC Converters · TSSOP-14L-EP
EA8961SCR from Everanalog IC design, in a TSSOP-14L-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog ground; the EP must be connected to AGND for heat dissipation. |
| 2 | PGND | power_in | Power ground; the input bypass capacitor must be placed directly across VIN and PGND (pins 3 and 2) close to the IC. |
| 3 | VIN | power_in | Power input with a 5V to 100V input voltage range; absolute maximum -0.3V to +100V. |
| 4 | EN/UVLO | input | Dual-level enable and UVLO input: below 0.35V is shutdown, 0.35V to 1.24V is standby, and above 1.24V allows switching once VCC exceeds 3.85V; absolute maximum -0.3V to +100V. |
| 5 | RON | input | On-time setting pin; a resistor connected from this pin to VIN sets the on-time and switching frequency; absolute maximum -0.3V to +100V. |
| 6 | SS | passive | Soft-start time setting pin; an external capacitor is charged by a 10µA source from 0V to 2V, and a minimum 1nF capacitor must be used; absolute maximum -0.3V to +7V. |
| 7 | NC | unconnected | Not connected. |
| 8 | FPWM | input | Mode select pin: connect to AGND for DCM at light load and to VCC for CCM; FPWM high input voltage is 3V minimum and low input voltage is 1V maximum; absolute maximum -0.3V to +7V. |
| 9 | FB | input | Feedback voltage input with a 2V reference (1.96V to 2.04V); absolute maximum -0.3V to +7V. |
| 10 | VCC | power_out | Internal high-voltage LDO output with 4.5V to 5.5V nominal range (5.0V typical), powering internal circuitry and charging the BST capacitor; absolute maximum -0.3V to +7V. |
| 11 | BST | power_in | Power input of the internal high-side N-MOSFET gate driver; BST to SW absolute maximum is +7V and BST to VCC absolute maximum is 100V. |
| 12 | SW | output | Switching output node; absolute maximum -1.5V to +100V, with -3V allowed for 20ns. |
| 13 | SW | output | Switching output node, bonded together with pin 12; absolute maximum -1.5V to +100V, with -3V allowed for 20ns. |
| 14 | NC | unconnected | Not connected. |
| 15 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Everanalog IC design |
| Package | TSSOP-14L-EP |
| Category | Power Management (PMIC) |
| Pins | 15 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC Voltage | VCC | 4.5 | 5 | 5.5 | V | ICC = 20mA | 4 |
| VCC Current | ICC | 30 | | | mA | | 4 |
| Shutdown Supply Current | ISD | | 35 | 60 | uA | VEN = 0V | 4 |
| Quiescent Current | IQ | | 1.3 | 2 | mA | VFB = 3V, ILOAD = 0A | 4 |
| Low Side MOSFET Souring Current Limit | ISOURCE-LM | 1.3 | 1.6 | 1.9 | A | | 4 |
| FB Pin Voltage Accuracy | VREF | 1.96 | 2 | 2.04 | V | | 5 |
| EN/UVLO Pin UVLO Voltage Threshold | VEN-TH | 1.2 | 1.24 | 1.27 | V | EN/UVLO Rising | 5 |
| EN/UVLO Pin Shutdown Mode Voltage Threshold | VEN-SD | | 0.29 | 0.35 | V | EN/UVLO Falling | 5 |
| EN/UVLO Pin Input Current | IEN | 15 | 20 | 25 | μA | EN/UVLO = 1.4V | 5 |
| UVLO Threshold | VUVLO | | 3.85 | | V | VCC Rising | 4 |
| UVLO Hysteresis | VUV-HYS | | 200 | | mV | | 4 |
| VIN-VCC Dropout Voltage | | | 600 | | mV | VIN = 5V, ICC = 20mA | 4 |
| High Side MOSFET On-Resistance | RDS(ON)-HM | | 300 | | mΩ | ISW = 0.5A | 4 |
| Low Side MOSFET On-Resistance | RDS(ON)-LM | | 150 | | mΩ | ISW = 0.5A | 4 |
| BST Pin UVLO Threshold | | | 2.9 | | V | | 4 |
| BST Pin UVLO Hysteresis | | | 200 | | mV | | 4 |
| High Side MOSFET Current Limit | ILIM-HM | | 1.61 | | A | | 4 |
| Low Side MOSFET Sinking Current Limit | ISINK-LM | | 3 | | A | | 4 |
| High Side MOSFET Current Limit Response Time | tLIM-HM | | 100 | | ns | ILIM-HM threshold detect to MOSFET turn off | 4 |
| High Side MOSFET Current Limit Turn off Time | tOFF | | 16.5 | | μs | FB = 0V, VIN = 72V | 4 |
| High Side MOSFET Current Limit Turn off Time | tOFF1 | | 13 | | μs | FB = 0.1V, VIN = 72V | 4 |
| High Side MOSFET Current Limit Turn off Time | tOFF2 | | 2.7 | | μs | FB = 1V, VIN = 72V | 4 |
| FPWM Pin Input High Voltage | VFPWM-H | | 3 | | V | | 4 |
| FPWM Pin Input Low Voltage | VFPWM-L | | 1 | | V | | 5 |
| Zero Current Detection | IZX | | 22.5 | | mA | FPWM = 0V | 5 |
| FB Pin Input Current | IFB | | 100 | | nA | | 5 |
| Soft-Start Current | ISS | | 10 | | μA | SS = 0.5V | 5 |
| EN/UVLO Pin Shutdown Mode Voltage Hysteresis | VEN-SD-TH | | 50 | | mV | | 5 |
| Thermal Shutdown Threshold | TOTP | | 175 | | °C | | 5 |
| Thermal Shutdown Hysteresis | THYS | | 20 | | °C | | 5 |
| Input Voltage (VIN) | VIN | -0.3 | | 100 | V | | 3 |
| EN/UVLO Pin Input Voltage | VEN | -0.3 | | 100 | V | | 3 |
| RON Pin Voltage | VRON | -0.3 | | 100 | V | | 3 |
| BST Pin Voltage | VBST | -0.3 | | 107 | V | | 3 |
| VCC Pin Voltage | VCC | -0.3 | | 7 | V | | 3 |
| FPWM Pin Voltage | VFPWM | -0.3 | | 7 | V | | 3 |
| SS Pin Voltage | VSS | -0.3 | | 7 | V | | 3 |
| FB Pin Voltage | VFB | -0.3 | | 7 | V | | 3 |
| SW Pin Voltage | VSW | -1.5 | | 100 | V | | 3 |
| BST Pin to SW Pin Voltage | | -0.3 | | 7 | V | | 3 |
| BST Pin to VCC Pin Voltage | | | | 100 | V | | 3 |
| SW Pin to AGND Pin Voltage | | -3 | | | V | 20ns | 3 |
| Ambient Temperature operating Range | TA | -40 | | 85 | °C | | 3 |
| Maximum Junction Temperature | TJmax | | | 150 | °C | | 3 |
| Lead Temperature (Soldering) | | | | 260 | °C | 10 sec | 3 |
| Storage Temperature Range | TS | -65 | | 150 | °C | | 3 |
| Minimum Soft-Start Capacitor | CSS | 1 | | | nF | In all applications | 10 |
| Minimum On-Time of RON | tON_min | 150 | | | ns | RON at maximum VIN | 11 |
| TSSOP14L-EP Power Dissipation (PDmax) | PDmax | | | 3.2 | W | TA=25°C | 3 |
| TSSOP14L-EP Thermal Resistance (θJC) | θJC | | 23.7 | | °C/W | | 3 |
| TSSOP14L-EP Thermal Resistance (θJA) | θJA | | 39.5 | | °C/W | | 3 |
## CAD (KiCad official)
- Symbol: `EA8961SCR`
- Footprint: `Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14L-EP (KiCad packages3D, STEP)
- 3D model files: `ea8961scr-etched.step` / `ea8961scr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ea8961scr.step` / `ea8961scr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Everanalog IC design datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590905429700386816) (19 pp, sha256 `da8e008f8e473fd1`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ea8961scr-datasheet.pdf)