# EA8421T6R

**Everanalog IC design** · DC-DC Converters · SOT-23-6

EA8421T6R from Everanalog IC design, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_in | Power input of the internal high-side N-MOSFET gate driver; connect a 100nF ceramic capacitor from BOOT to SWITCH, with BOOT-to-SWITCH limited to VSWITCH-0.3V to VSWITCH+5V. |
| 2 | GND | power_in | Ground pin. |
| 3 | FBK | input | Feedback input; connect a voltage divider from VOUT to FBK and GND to set the output voltage (VREF 0.8V), with FBK pin voltage rated -0.3V to +6V. |
| 4 | RUN | input | On/off control input where VRUN above 2V enables the regulator and below 0.4V shuts it down; it must not be left floating and can be tied to PWR through 150kΩ for automatic startup, with a rating of -0.3V to +40V. |
| 5 | PWR | power_in | Input supply pin, operating from 5V to 40V, with a 10uF MLCC recommended between PWR and GND. |
| 6 | SWITCH | output | Internal MOSFET switching output that feeds the low-pass output filter (inductor and output capacitor), rated -1V to +45V and a high-current noise node. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Everanalog IC design |
| Package | SOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VPWR | 5 |  | 40 | V |  | 4 |
| Shutdown Supply Current | ISD |  | 2 | 10 | uA | VRUN = 0V | 4 |
| Shutdown Supply Current | ISD |  |  | 20 | uA | TJ = -55°C to 125°C | 4 |
| Quiescent Current | IQ |  | 400 | 600 | uA | VRUN = 2V, VFBK = 105% VREF, ILOAD = 0A | 4 |
| Quiescent Current | IQ |  |  | 1 | mA | TJ = -55°C to 125°C | 4 |
| Reference Voltage | VREF | 0.784 | 0.8 | 0.816 | V | 5V ≤ VPWR ≤ 40V | 4 |
| High Side MOSFET On-Resistance | RDS(ON)-HM |  |  | 400 | mΩ |  | 4 |
| Low Side MOSFET On-Resistance | RDS(ON)-LM |  |  | 250 | mΩ |  | 4 |
| High Side MOSFET Current Limit | ILIM-HM |  |  | 2 | A |  | 4 |
| High Side MOSFET Leakage Current | ILEAK-HM |  |  | 10 | uA | VRUN = 0V, VSWITCH = 0V | 4 |
| RUN Pin Input Low Voltage | VRUN-L |  |  | 0.4 | V |  | 4 |
| RUN Pin Input High Voltage | VRUN-H | 2 |  |  | V |  | 4 |
| Maximum Duty Cycle | DMAX |  |  | 92 | % |  | 4 |
| High Side MOSFET Minimum On Time | TONMIN |  |  | 80 | ns |  | 4 |
| Thermal Shutdown Threshold | TOTP |  |  | 160 | °C |  | 4 |
| Switching Frequency | FSW |  | 600 |  | KHz |  | 4 |
| RUN Pin Pull-Low Resistance | RRUN |  | 950 |  | KΩ |  | 4 |
| Internal Soft-Start Time |  |  | 1 |  | ms |  | 4 |
| Input Voltage (VPWR) absolute maximum | VPWR | -0.3 |  | 45 | V |  | 3 |
| RUN Pin Input Voltage (VRUN) absolute maximum | VRUN | -0.3 |  | 45 | V |  | 3 |
| SWITCH Pin Voltage | VSWITCH | -1 |  | 45 | V |  | 3 |
| FBK Pin Voltage | VFBK | -0.3 |  | 6 | V |  | 3 |
| Junction Temperature Range | TJ | -55 |  | 125 | °C |  | 3 |
| Maximum Junction Temperature | TJmax |  |  | 150 | °C |  | 3 |
| Lead Temperature (Soldering) |  |  |  | 260 | °C | 10 sec soldering | 3 |
| Storage Temperature Range | TS | -65 |  | 150 | °C |  | 3 |
| ESD (HBM) |  |  |  | 2 | KV | HBM | 3 |
| Input Voltage (VPWR) recommended | VPWR | 5 |  | 40 | V |  | 3 |
| RUN Pin Input Voltage (VRUN) recommended | VRUN | -0.3 |  | 40 | V |  | 3 |
| SOT-23-6 Thermal Resistance (junction-to-case) | θJC |  | 125 |  | °C/W |  | 3 |
| SOT-23-6 Thermal Resistance (junction-to-ambient) | θJA |  | 250 |  | °C/W |  | 3 |
| SOT-23-6 Power Dissipation at TA=25°C | PDmax |  |  | 0.5 | W | TA = 25°C | 3 |

## CAD (KiCad official)

- Symbol: `EA8421T6R`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `ea8421t6r-etched.step` / `ea8421t6r-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ea8421t6r.step` / `ea8421t6r.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Everanalog IC design datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590454570699681792) (9 pp, sha256 `0ab11ff8c86d7383`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ea8421t6r-datasheet.pdf)