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EA8107E5

Public Made by Adom

by adom

Everanalog IC design DC-DC Converters, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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EA8107E5

Everanalog IC design · DC-DC Converters · SOT-23-5

EA8107E5 from Everanalog IC design, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable control pin; pull high to turn the IC on and low to disable it (shutdown current below 1µA), and do not leave it floating.
2 GND power_in Ground pin.
3 LX passive Power switching node to which the external inductor is connected.
4 VIN power_in Power supply input pin (2.5V to 6V operating range); place input capacitors as close as possible from VIN to GND.
5 FB input Voltage feedback input connected to VOUT through a resistive divider; the IC regulates it at 0.6V.

Key specifications

Parameter Value
Manufacturer Everanalog IC design
Package SOT-23-5
Category Power Management
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Supply Voltage VIN 2.5 6 V 5
Reference Voltage VREF 0.588 0.6 0.612 V VIN=5V, VOUT=2.5V, TA=25°C 5
Oscillation Frequency FOSC 1.2 1.5 1.8 MHz 5
Shutdown Current ISHDN 0.1 1 μA EN=0V 5
FB Input Leakage Current IFB 0.01 1 µA VFB=VIN 5
Quiescent Current Iq 200 μA VFB=0.65V, IOUT=0A 5
EN High-Level Input Voltage VEN(H) 1.5 V 5
EN Low-Level Input Voltage VEN(L) 0.4 V 5
EN Input Current IEN 2.5 µA 5
P-Channel Current Limit ILIM 1.5 A Guarantee by design 5
Input Over Voltage Protection VIN OVP 6.3 V 5
P-Channel MOSFET On-Resistance RDS(ON) 330 mΩ Guarantee by design 5
N-Channel MOSFET On-Resistance RDS(ON) 200 mΩ Guarantee by design 5
Under Voltage Lockout Voltage UVLO 2.4 V 5
UVLO Hysteresis VHYS 0.3 V 5
Minimum On Time 50 ns 5
Maximum Duty Cycle 100 % 5
Internal Soft Start Time TSS 1 ms 5
PG Rising Threshold VPG (H) 90 % VFB Rising 5
PG Low Threshold VPG (L) 85 % VFB falling 5
PG Sink Current IPG 1 mA VPG=0.1V 5
LX Discharge Resistance 100 Ω 5
Thermal Shutdown Temperature TSD 150 °C Guarantee by design 5
VIN to GND VIN -0.3 6.5 V 4
Dynamic LX Voltage LX -4.5 7.5 V in 20ns Duration 4
EN, FB, PG to GND -0.3 6.5 V -0.3V to VIN; max printed as VIN 4
Package Thermal Resistance θJA SOT-23-5 θJA 250 °C/W 4-layer JEDEC-51-7 board, 25°C ambient 4
Package Thermal Resistance θJC SOT-23-5 θJC 130 °C/W 4
Maximum Junction Temperature TJ 150 °C 4
Lead Temperature 260 °C Soldering, 10sec. 4
Storage Temperature TS -65 150 °C 4
Supply Voltage VIN 2.5 6 V 4
Operation Temperature Range TOPR -40 85 °C 4

CAD (KiCad official)

  • Symbol: EA8107E5
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: ea8107e5-etched.step / ea8107e5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ea8107e5.step / ea8107e5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Everanalog IC design datasheet (14 pp, sha256 829f9791682d7dbc, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF