component
EA8105AT5R
Public Made by Adomby adom
Everanalog IC design DC-DC Converters, SOT23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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EA8105AT5R
Everanalog IC design · DC-DC Converters · SOT23-5
EA8105AT5R from Everanalog IC design, in a SOT23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable control pin: pull high to turn the IC on and pull low to disable it, with VEN(H) minimum 1.5V and VEN(L) maximum 0.4V, and it must not be left floating. |
| 2 | GND | power_in | Ground pin. |
| 3 | LX | output | Power switching node that connects to the inductor and the drains of the internal high-side PMOS and low-side NMOS. |
| 4 | VIN | power_in | Power supply input pin, with a supply range of 2.5V to 6.5V; input capacitors should be placed as close as possible from VIN to GND. |
| 5 | FB | input | Voltage feedback input connected to VOUT through a resistive divider; the IC regulates FB at 0.6V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Everanalog IC design |
| Package | SOT23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND | -0.3 | 7 | V | 4 | |||
| LX to GND | -0.3 | V | upper limit printed as VIN+0.3V | 4 | |||
| EN, FB, PG to GND | -0.3 | V | upper limit printed as VIN | 4 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 4 | |||
| Lead Temperature (Soldering, 10sec.) | 260 | °C | 10 sec soldering | 4 | |||
| Storage Temperature | TS | -65 | 150 | °C | 4 | ||
| Supply Voltage | VIN | 2.5 | 6.5 | V | 4 | ||
| Junction Temperature Range | -40 | 125 | °C | 4 | |||
| Operation Temperature Range | TOPR | -40 | 85 | °C | 4 | ||
| Input Supply Voltage | VIN | 2.5 | 6.5 | V | 5 | ||
| Shutdown Current | ISHDN | 0.1 | 1 | μA | EN=GND | 5 | |
| Reference Voltage | VREF | 0.588 | 0.6 | 0.612 | V | 5 | |
| FB Input Leakage Current | IFB | 0.01 | 1 | µA | VFB=VIN | 5 | |
| Oscillation Frequency | FOSC | 0.8 | 1 | 1.2 | MHz | IOUT=300mA | 5 |
| P-Channel Current Limit | ILIM | 2.2 | 2.75 | A | 5 | ||
| Maximum Duty Cycle | 100 | % | 5 | ||||
| Minimum On Time | 50 | ns | 5 | ||||
| Input Over Voltage Protection | VIN OVP | 6.3 | V | 5 | |||
| Quiescent Current | Iq | 200 | μA | VFB=0.65V, IOUT=0A | 5 | ||
| P-Channel MOSFET On-Resistance | RDS(ON) | 130 | mΩ | 5 | |||
| N-Channel MOSFET On-Resistance | RDS(ON) | 80 | mΩ | 5 | |||
| EN High-Level Input Voltage | VEN(H) | 1.5 | V | 5 | |||
| EN Low-Level Input Voltage | VEN(L) | 0.4 | V | 5 | |||
| Under Voltage Lockout Voltage | UVLO | 2.4 | V | 5 | |||
| UVLO Hysteresis | VHYS | 0.2 | V | 5 | |||
| Internal Soft-Start Time | TSS | 1 | ms | 5 | |||
| VOUT Discharge Resistance | 95 | Ω | 5 | ||||
| Thermal Shutdown Temperature | TSD | 150 | °C | 5 | |||
| Thermal Resistance Junction-to-Ambient, SOT-23-5 | θJA | 250 | °C/W | Note 2: 25°C ambient, JEDEC-51-7 test board | 4 | ||
| Thermal Resistance Junction-to-Case, SOT-23-5 | θJC | 130 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
EA8105AT5R - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT23-5 (KiCad packages3D, STEP)
- 3D model files:
ea8105at5r-etched.step/ea8105at5r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ea8105at5r.step/ea8105at5r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Everanalog IC design datasheet (10 pp, sha256
376b856922403942, retrieved 2026-11-04, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# EA8105AT5R
**Everanalog IC design** · DC-DC Converters · SOT23-5
EA8105AT5R from Everanalog IC design, in a SOT23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable control pin: pull high to turn the IC on and pull low to disable it, with VEN(H) minimum 1.5V and VEN(L) maximum 0.4V, and it must not be left floating. |
| 2 | GND | power_in | Ground pin. |
| 3 | LX | output | Power switching node that connects to the inductor and the drains of the internal high-side PMOS and low-side NMOS. |
| 4 | VIN | power_in | Power supply input pin, with a supply range of 2.5V to 6.5V; input capacitors should be placed as close as possible from VIN to GND. |
| 5 | FB | input | Voltage feedback input connected to VOUT through a resistive divider; the IC regulates FB at 0.6V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Everanalog IC design |
| Package | SOT23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND | | -0.3 | | 7 | V | | 4 |
| LX to GND | | -0.3 | | | V | upper limit printed as VIN+0.3V | 4 |
| EN, FB, PG to GND | | -0.3 | | | V | upper limit printed as VIN | 4 |
| Maximum Junction Temperature | TJ | | | 150 | °C | | 4 |
| Lead Temperature (Soldering, 10sec.) | | | | 260 | °C | 10 sec soldering | 4 |
| Storage Temperature | TS | -65 | | 150 | °C | | 4 |
| Supply Voltage | VIN | 2.5 | | 6.5 | V | | 4 |
| Junction Temperature Range | | -40 | | 125 | °C | | 4 |
| Operation Temperature Range | TOPR | -40 | | 85 | °C | | 4 |
| Input Supply Voltage | VIN | 2.5 | | 6.5 | V | | 5 |
| Shutdown Current | ISHDN | | 0.1 | 1 | μA | EN=GND | 5 |
| Reference Voltage | VREF | 0.588 | 0.6 | 0.612 | V | | 5 |
| FB Input Leakage Current | IFB | | 0.01 | 1 | µA | VFB=VIN | 5 |
| Oscillation Frequency | FOSC | 0.8 | 1 | 1.2 | MHz | IOUT=300mA | 5 |
| P-Channel Current Limit | ILIM | 2.2 | | 2.75 | A | | 5 |
| Maximum Duty Cycle | | | | 100 | % | | 5 |
| Minimum On Time | | 50 | | | ns | | 5 |
| Input Over Voltage Protection | VIN OVP | | 6.3 | | V | | 5 |
| Quiescent Current | Iq | | 200 | | μA | VFB=0.65V, IOUT=0A | 5 |
| P-Channel MOSFET On-Resistance | RDS(ON) | | 130 | | mΩ | | 5 |
| N-Channel MOSFET On-Resistance | RDS(ON) | | 80 | | mΩ | | 5 |
| EN High-Level Input Voltage | VEN(H) | | 1.5 | | V | | 5 |
| EN Low-Level Input Voltage | VEN(L) | | 0.4 | | V | | 5 |
| Under Voltage Lockout Voltage | UVLO | | 2.4 | | V | | 5 |
| UVLO Hysteresis | VHYS | | 0.2 | | V | | 5 |
| Internal Soft-Start Time | TSS | | 1 | | ms | | 5 |
| VOUT Discharge Resistance | | | 95 | | Ω | | 5 |
| Thermal Shutdown Temperature | TSD | | 150 | | °C | | 5 |
| Thermal Resistance Junction-to-Ambient, SOT-23-5 | θJA | | 250 | | °C/W | Note 2: 25°C ambient, JEDEC-51-7 test board | 4 |
| Thermal Resistance Junction-to-Case, SOT-23-5 | θJC | | 130 | | °C/W | | 4 |
## CAD (KiCad official)
- Symbol: `EA8105AT5R`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT23-5 (KiCad packages3D, STEP)
- 3D model files: `ea8105at5r-etched.step` / `ea8105at5r-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ea8105at5r.step` / `ea8105at5r.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Everanalog IC design datasheet](docs/ea8105at5r-datasheet.pdf) (10 pp, sha256 `376b856922403942`, retrieved 2026-11-04, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ea8105at5r-datasheet.pdf)