EA8103T5R
Public Made by Adomby adom
Everanalog IC design DC-DC Converters, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
EA8103T5R
Everanalog IC design · DC-DC Converters · SOT-23-5
EA8103T5R from Everanalog IC design, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RUN | input | Enable / on-off control input. Drive above 1.5V to turn the converter on, drive below 0.4V to turn it off. Absolute maximum input voltage is -0.3V to +7V. Must not be left floating. |
| 2 | GND | power_in | Device ground return. Connect to the system ground plane; also serves as the low-side reference for the input and output capacitors and the feedback divider. |
| 3 | SWITCH | output | Power switching node output between the internal high-side PMOS and low-side NMOS. Connect to the output inductor (typ. 1uH to 4.7uH). Absolute maximum swing is -0.3V to (VPWR+0.3V); this is a high-current, high dv/dt noise node so keep traces short and wide. |
| 4 | PWR | power_in | Power input supply pin, 2.6V to 6V (absolute maximum +7V, OVP threshold ~7V). Bypass with a 10uF X5R/X7R MLCC placed as close to the pin as possible; provides current to the internal high-side PMOS (RDS(ON) ~200mΩ, current limit 1.8-2.4A). |
| 5 | FBK | input | Feedback input to the internal error amplifier. Connect a resistor divider from VOUT to FBK to GND to set the output voltage; regulated to VREF = 1.13V (1.107V-1.153V). Leakage current is +/-1uA max. Absolute maximum is -0.3V to +7V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Everanalog IC design |
| Package | SOT-23-5 |
| Category | PMIC |
| Pins | 5 |
Ordering variants
Same part, different packaging or reel option.
EA8103T5R
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VPWR | 2.6 | 6 | V | 4 | ||
| UVLO Threshold | VUVLO | 2.2 | 2.35 | 2.5 | V | VPWR Rising | 4 |
| Reference Voltage | VREF | 1.107 | 1.13 | 1.153 | V | 4 | |
| PMOS Current Limit | ILIM-P | 1.8 | 2.4 | A | 4 | ||
| Shutdown Supply Current | ISD | 0.1 | 1 | uA | VRUN = 0V | 4 | |
| SWITCH Leakage Current | ILEAK-SWITCH | -1 | 1 | uA | VPWR = 5V, VRUN = 0V, VSWITCH = 0V or 5V | 4 | |
| FBK Leakage Current | ILEAK-FBK | -1 | 1 | uA | VFB = VPWR | 4 | |
| Input Supply Voltage (recommended) | VPWR | 2.6 | 6 | V | 3 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 3 | ||
| Input Supply Voltage (absolute max) | VPWR | -0.3 | 7 | V | 3 | ||
| RUN Pin Input Voltage | VRUN | -0.3 | 7 | V | 3 | ||
| SWITCH Pin Voltage | VSWITCH | -0.3 | V | Max printed as VPWR+0.3V | 3 | ||
| FBK Pin Voltage | VFBK | -0.3 | 7 | V | 3 | ||
| Ambient Temperature operating Range | TA | -40 | 85 | °C | 3 | ||
| Maximum Junction Temperature | TJmax | 150 | °C | 3 | |||
| Storage Temperature Range | TS | -65 | 150 | °C | 3 | ||
| Lead Temperature (Soldering) | 260 | °C | 10 sec | 3 | |||
| SOT-23-5 Thermal Resistance (θJC) | θJC | 125 | °C/W | 3 | |||
| SOT-23-5 Thermal Resistance (θJA) | θJA | 250 | °C/W | 3 | |||
| SOT-23-5 Power Dissipation | PDmax | 0.5 | W | TA=25°C | 3 | ||
| Quiescent Current | IQ | 1 | uA | VRUN = 2V, VFB = 1.2V | 4 | ||
| UVLO Hysteresis | VUV-HYS | 0.1 | V | 4 | |||
| Output Load Current | ILOAD | 1.2 | A | 4 | |||
| Switching Frequency | FSW | 1.35 | MHz | ILOAD = 100mA | 4 | ||
| PMOS On-Resistance | RDS(ON)-P | 200 | mΩ | ILOAD = 100mA | 4 | ||
| NMOS On-Resistance | RDS(ON)-N | 300 | mΩ | ILOAD = 100mA | 4 | ||
| RUN Pin Input Low Voltage | VRUN-L | 0.4 | V | 4 | |||
| RUN Pin Input High Voltage | VRUN-H | 1.5 | V | 4 | |||
| Input Over-Voltage Protection Threshold | VOVP | 7 | V | 4 | |||
| Input Over-Voltage Protection Hysteresis | VOVP-HYS | 0.3 | V | 4 | |||
| Thermal Shutdown Threshold | TOTP | 160 | °C | 4 |
CAD (KiCad official)
- Symbol:
EA8103T5R - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
ea8103t5r-etched.step/ea8103t5r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ea8103t5r.step/ea8103t5r.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
ea8103t5r.step |
85 KB | You want the bare part, or you mark your own boards. |
ea8103t5r-etched.step |
1.9 MB | You want the part with EA8103T5R already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 459 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Everanalog IC design datasheet (8 pp, sha256
a91baf5d66011f05, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).