component
DX5011CT
Public Made by Adomby adom
Dersem AC-DC Controllers And Regulators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 1mo ago |
| viewers | 1mo ago |
| dx5011ct-etched.glb | 1mo ago |
| dx5011ct-etched.step | 1mo ago |
| dx5011ct-hero.glb | 1mo ago |
| dx5011ct-hero.overlay.json | 1mo ago |
| dx5011ct.glb | 1mo ago |
| dx5011ct.kicad_mod | 1mo ago |
| dx5011ct.kicad_sym | 1mo ago |
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| dx5011ct.step | 1mo ago |
| package.json | 1mo ago |
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| README.md | 1mo ago |
DX5011CT
Dersem · AC-DC Controllers And Regulators · SOP-8
DX5011CT from Dersem, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Peak current sense input: when the sensed voltage exceeds the peak current threshold (0.50 to 0.60 V, typical 0.55 V), the internal power MOSFET turns off immediately, with 350 ns leading-edge blanking and an abnormal overcurrent threshold of 0.9 V. |
| 2 | VDD | power_in | Chip supply pin, which also serves as the output voltage feedback input when FB is floating; a 1 uF ceramic capacitor is recommended, VDD_ON is 7.5 V, VDD_OFF is 7.0 V, VDD overvoltage protection is 28 V, and the internal clamp is 30 V at 10 mA. |
| 3 | GND | power_in | Chip ground. |
| 4 | FB | input | Feedback input with a 2.0 V internal reference (1.97 to 2.03 V); leaving it floating selects the default 12 V output, the output overvoltage threshold is 2.4 V, the overload threshold is 1.87 V, and the pin voltage range is -0.3 to 7 V. |
| 5 | Drain | power_in | Drain of the internal 500 V high-voltage power MOSFET, which also feeds the high-voltage startup circuit; the Drain pin voltage is rated -0.3 to 500 V. |
| 6 | Drain | power_in | Drain of the internal 500 V high-voltage power MOSFET, which also feeds the high-voltage startup circuit; the Drain pin voltage is rated -0.3 to 500 V. |
| 7 | Drain | power_in | Drain of the internal 500 V high-voltage power MOSFET, which also feeds the high-voltage startup circuit; the Drain pin voltage is rated -0.3 to 500 V. |
| 8 | Drain | power_in | Drain of the internal 500 V high-voltage power MOSFET, which also feeds the high-voltage startup circuit; the Drain pin voltage is rated -0.3 to 500 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Dersem |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
DX5011CT - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
dx5011ct-etched.step/dx5011ct-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dx5011ct.step/dx5011ct.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Dersem datasheet (11 pp, sha256
e5852b540aaa6ea5, retrieved 2026-10-09, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).