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DTS4500-VB

VBsemi Elec · MOSFETs · SOT-23(TO-236)

DTS4500-VB from VBsemi Elec, in a SOT-23(TO-236). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol and footprint from KiCad-official CAD; the 3D model is generated from the datasheet's package dimensions.

Pinout

Pin Name Type Function
1 G input Gate terminal; gate-source voltage VGS is limited to ±20 V, and the gate-source threshold VGS(th) is specified at 0.7 V to 2.0 V with VDS = VGS and ID = 250 µA.
2 S passive Source terminal; the continuous source-drain diode current IS is 1.4 A at TC = 25 °C, and the body diode forward voltage VSD is 0.8 V to 1.2 V at IS = 2.7 A, VGS = 0 V.
3 D passive Drain terminal; the drain-source voltage VDS is limited to 30 V, with a continuous drain current ID of 6.5 A at TC = 25 °C (package limited).

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package SOT-23(TO-236)
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS 30 V 1
Gate-Source Voltage VGS -20 20 V 1
Continuous Drain Current ID 6.5 A TC = 25 °C (TJ = 150 °C) 1
Continuous Drain Current ID 6 A TC = 70 °C 1
Continuous Drain Current ID 5.3 A TA = 25 °C 1
Continuous Drain Current ID 5 A TA = 70 °C 1
Pulsed Drain Current IDM 25 A 1
Continuous Source-Drain Diode Current IS 1.4 A TC = 25 °C 1
Maximum Power Dissipation PD 1.7 W TC = 25 °C 1
Maximum Power Dissipation PD 1.1 W TC = 70 °C 1
Maximum Power Dissipation PD 0.7 W TA = 70 °C, notes b, c 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Soldering Recommendations (Peak Temperature) 260 °C Notes d, e 1
Maximum Junction-to-Ambient RthJA 90 115 °C/W t ≤ 5 s 1
Maximum Junction-to-Foot (Drain) RthJF 60 75 °C/W Steady State 1
Maximum Junction-to-Ambient RthJA 130 °C/W Steady state conditions, note d 1
Drain-Source Breakdown Voltage VDS 30 V VGS = 0 V, ID = 250 µA 2
Gate-Source Threshold Voltage VGS(th) 0.7 2 V VDS = VGS, ID = 250 µA 2
Gate-Source Leakage IGSS -100 100 nA VDS = 0 V, VGS = ±20 V 2
Zero Gate Voltage Drain Current IDSS 1 µA VDS = 30 V, VGS = 0 V 2
Zero Gate Voltage Drain Current IDSS 10 µA VDS = 30 V, VGS = 0 V, TJ = 55 °C 2
On-State Drain Current ID(on) 10 A VDS ≥ 5 V, VGS = 10 V 2
Drain-Source On-State Resistance RDS(on) 0.03 Ω VGS = 10 V, ID = 3.2 A 2
Drain-Source On-State Resistance RDS(on) 0.033 Ω VGS = 4.5 V, ID = 2.8 A 2
Total Gate Charge Qg 4.5 6.7 nC VDS = 15 V, VGS = 10 V, ID = 3.4 A 2
Total Gate Charge Qg 2.1 3.2 nC VDS = 15 V, VGS = 4.5 V, ID = 3.4 A 2
Gate Resistance Rg 0.8 4.4 8.8 Ω f = 1 MHz 2
Turn-On Delay Time td(on) 12 20 ns VDD = 15 V, RL = 5.6 Ω, ID ≅ 2.7 A, VGEN = 4.5 V, Rg = 1 Ω 2
Rise Time tr 50 75 ns VDD = 15 V, RL = 5.6 Ω, ID ≅ 2.7 A, VGEN = 4.5 V, Rg = 1 Ω 2
Turn-Off Delay Time td(off) 12 20 ns VDD = 15 V, RL = 5.6 Ω, ID ≅ 2.7 A, VGEN = 4.5 V, Rg = 1 Ω 2
Fall Time tf 22 35 ns VDD = 15 V, RL = 5.6 Ω, ID ≅ 2.7 A, VGEN = 4.5 V, Rg = 1 Ω 2
Turn-On Delay Time td(on) 5 10 ns VDD = 15 V, RL = 5.6 Ω, ID ≅ 2.7 A, VGEN = 10 V, Rg = 1 Ω 2
Rise Time tr 12 20 ns VDD = 15 V, RL = 5.6 Ω, ID ≅ 2.7 A, VGEN = 10 V, Rg = 1 Ω 2
Turn-Off Delay Time td(off) 10 15 ns VDD = 15 V, RL = 5.6 Ω, ID ≅ 2.7 A, VGEN = 10 V, Rg = 1 Ω 2
Fall Time tf 5 10 ns VDD = 15 V, RL = 5.6 Ω, ID ≅ 2.7 A, VGEN = 10 V, Rg = 1 Ω 2
Continuous Source-Drain Diode Current IS 1.4 A TC = 25 °C 2
Pulse Diode Forward Current ISM 15 A 2
Body Diode Voltage VSD 0.8 1.2 V IS = 2.7 A, VGS = 0 V 2
Body Diode Reverse Recovery Time trr 10 20 ns IF = 2.7 A, dI/dt = 100 A/µs, TJ = 25 °C 2
Body Diode Reverse Recovery Charge Qrr 5 10 nC IF = 2.7 A, dI/dt = 100 A/µs, TJ = 25 °C 2

CAD (land: KiCad; 3D: generated from the datasheet)

  • Symbol: DTS4500-VB
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23(TO-236), generated on the KiCad land (body 1.3 x 2.92 mm, terminals on the pads, 1.0050000000000001 mm tall, datasheet A, midpoint of min and max). KiCad's stock model for this land is taller than the datasheet allows, so the model is generated from the datasheet drawing; the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
  • 3D model files: dts4500-vb-etched.step / dts4500-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dts4500-vb.step / dts4500-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (9 pp, sha256 570969a5a4059ffe, retrieved 2026-11-13, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: land: KiCad official libraries (CC-BY-SA 4.0); 3D: generated from the datasheet's package dimensions (provenance.model_3d_generated).

Datasheet PDF