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Ray Publish 0.1.0 2d3415f 11d ago

DT1452-02SOQ-7

Diodes Incorporated · TVS · SOT-23

DT1452-02SOQ-7 from Diodes Incorporated, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I/O 1 passive ESD-protected channel 1 input/output, clamped to VSS with 1.2pF typical capacitance, VBR 7V min, 12A peak pulse (8/20µs) and ±16kV IEC61000-4-2 contact/air.
2 I/O 2 passive ESD-protected channel 2 input/output, clamped to VSS with 1.2pF typical capacitance, VBR 7V min, 12A peak pulse (8/20µs) and ±16kV IEC61000-4-2 contact/air.
3 VSS power_in Common reference/ground pin of the TVS array to which both I/O channels are clamped.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-23
Category TVS/Fuse/Board Level Protection
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Reverse Working Voltage VRWM 5.5 V 2
Reverse Leakage Current IR 1 μA VR = 5.5V, I/O to VSS 2
Reverse Breakdown Voltage VBR 7 10 V IR = 1mA, I/O to VSS 2
Forward Voltage VF 0.85 1.1 V IF = 15mA, VSS to I/O 2
Channel Input Capacitance CI/O 1.2 1.7 pF VR = 2.5V, f = 1MHz 2
Reverse Clamping Voltage VC 7.5 V IPP = 5A, I/O to VSS, 8/20µs 2
Reverse Clamping Voltage VC 9.5 V IPP = 12A, I/O to VSS, 8/20µs 2
ESD Clamping Voltage VESD 11 V TLP, 20A, tP = 100ns, I/O to VSS, Per Figure 7 2
Dynamic Resistance RDIF 0.22 Ω TLP, 20A, tP = 100ns, I/O to VSS, Per Figure 7 2
Variation of Channel Input Capacitance CI/O 0.03 pF VSS = 0V, I/O = 2.5V, f =1MHz, I/O_x to VSS, I/O_y to VSS 2
Peak Pulse Current IPP_I/O 12 A I/O to VSS, 8/20µs 2
ESD Protection, Contact Discharge VESD_I/O_CONTACT -16 16 kV I/O to VSS, Per IEC61000-4-2 2
ESD Protection, Air Discharge VESD_I/O_AIR -16 16 kV I/O to VSS, Per IEC61000-4-2 2
Power Dissipation PD 300 mW Note 5, device mounted on FR-4 PCB 2
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 2
Thermal Resistance, Junction to Ambient RθJA 417 °C/W Note 5, device mounted on FR-4 PCB 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin  Terminals: Matte Tin Finish Annealed over Alloy 42 Leadframe (Lead-Free Plating). Solderable per MIL-STD-202, Method 208 1

CAD (KiCad official)

  • Symbol: DT1452-02SOQ-7
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: dt1452-02soq-7-etched.step / dt1452-02soq-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dt1452-02soq-7.step / dt1452-02soq-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (5 pp, sha256 b4b6579cd324cc12, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF