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DT1240V3-04SO-7

Diodes Incorporated · ESD And Surge Protection (TVS/ESD) · SOT-26

DT1240V3-04SO-7 from Diodes Incorporated, in a SOT-26. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I/O1 passive ESD-protected high-speed I/O channel 1, clamped to VSS with 0.55pF typical capacitance and VBR of 6V minimum.
2 VSS power_in Ground reference (VSS) for all four TVS channels, to which I/O pins are clamped.
3 I/O2 passive ESD-protected high-speed I/O channel 2, clamped to VSS with 0.55pF typical capacitance and VBR of 6V minimum.
4 I/O3 passive ESD-protected high-speed I/O channel 3, clamped to VSS with 0.55pF typical capacitance and VBR of 6V minimum.
5 N/A unconnected Not used; marked N/A on the device schematic with no internal connection shown.
6 I/O4 passive ESD-protected high-speed I/O channel 4, clamped to VSS with 0.55pF typical capacitance and VBR of 6V minimum.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-26
Category Circuit Protection
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Peak Pulse Current, per IEC 61000-4-5 IPP 5.5 A I/O to VSS, 8/20µs 2
Peak Pulse Power, per IEC 61000-4-5 PPP 60 W I/O to VSS, 8/20µs 2
ESD Protection, Contact Discharge, per IEC 61000-4-2 VESD_CONTACT -14 14 kV I/O to VSS 2
ESD Protection, Air Discharge, per IEC 61000-4-2 VESD_AIR -16 16 kV I/O to VSS 2
Operating Temperature TOP -55 85 °C 2
Storage Temperature TSTG -55 150 °C 2
Reverse Working Voltage VRWM 3.3 V 2
Reverse Current IR 0.5 μA VR = 3.3V, I/O to VSS 2
Reverse Breakdown Voltage VBR 6 V IR = 1mA, I/O to VSS 2
Forward Clamping Voltage VF -1 -0.85 V IF = -15mA, I/O to VSS 2
Reverse Clamping Voltage VC 9 11 V IPP = 5.5A, I/O to VSS, 8/20µs 2
Trigger Voltage VTRIG 9.5 V 2
Channel Input Capacitance CI/O 0.55 0.65 pF VI/O = 2.5V, VSS = 0V, f = 1MHz 2
Power Dissipation PD 300 mW Typical; Note 5 (FR-4 PCB, 2oz copper pad layout) 2
Thermal Resistance, Junction to Ambient RJA 417 °C/W Typical; Note 5 (FR-4 PCB, 2oz copper pad layout) 2
ESD Clamping Voltage VESD 8.8 V TLP, 10A, tP = 100ns, I/O to VSS 2
Dynamic Reverse Resistance RDIF-R 0.3 Ω TLP, 10A, tP = 100ns, I/O to VSS 2
Dynamic Forward Resistance RDIF-F 0.25 Ω TLP, 10A, tP = 100ns, VSS to I/O 2
Delta CI/O 0.04 pF CI/OMAX-CI/OMIN 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin  Terminal Connections: See Schematic  Terminals, Finish, Matte Tin Pleated Leads; 1

CAD (KiCad official)

  • Symbol: DT1240V3-04SO-7
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-26 (KiCad packages3D, STEP)
  • 3D model files: dt1240v3-04so-7-etched.step / dt1240v3-04so-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dt1240v3-04so-7.step / dt1240v3-04so-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (6 pp, sha256 049bdac5b056e95d, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF