component
dsPIC33FJ64GS406-I
Public Made by Adomby adom
Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
Publish 0.1.0
9612fce
dsPIC33FJ64GS406-I
Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-64-EP(9x9)
dsPIC33FJ64GS406-I from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PWM3H/RE5 | bidirectional | PORTE I/O shared with PWM3 high output. |
| 2 | PWM4L/RE6 | bidirectional | PORTE I/O shared with PWM4 low output. |
| 3 | PWM4H/RE7 | bidirectional | PORTE I/O shared with PWM4 high output. |
| 4 | SCK2/FLT12/CN8/RG6 | bidirectional | PORTG I/O with SPI2 serial clock, PWM Fault 12 input and change notification 8. |
| 5 | SDI2/FLT11/CN9/RG7 | bidirectional | PORTG I/O with SPI2 data in, PWM Fault 11 input and change notification 9. |
| 6 | SDO2/FLT10/CN10/RG8 | bidirectional | PORTG I/O with SPI2 data out, PWM Fault 10 input and change notification 10. |
| 7 | MCLR | input | Master Clear active-low Reset input to the device, also used for programming and debugging. |
| 8 | SS2/FLT9/SYNCI2/CN11/RG9 | bidirectional | PORTG I/O with SPI2 slave select, PWM Fault 9, PWM external synchronization input 2 and change notification 11. |
| 9 | VSS | power_in | Ground reference for logic and I/O pins. |
| 10 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V). |
| 11 | AN5/AQEB1/CN7/RB5 | bidirectional | PORTB I/O with analog input 5, alternate QEI1 phase B input and change notification 7. |
| 12 | AN4/AQEA1/CN6/RB4 | bidirectional | PORTB I/O with analog input 4, alternate QEI1 phase A input and change notification 6. |
| 13 | AN3/AINDX1/CN5/RB3 | bidirectional | PORTB I/O with analog input 3, alternate QEI1 index input and change notification 5. |
| 14 | AN2/ASS1/CN4/RB2 | bidirectional | PORTB I/O with analog input 2, alternate SPI1 slave select and change notification 4. |
| 15 | PGEC3/AN1/CN3/RB1 | bidirectional | PORTB I/O with analog input 1, programming/debugging clock channel 3 and change notification 3. |
| 16 | PGED3/AN0/CN2/RB0 | bidirectional | PORTB I/O with analog input 0, programming/debugging data channel 3 and change notification 2. |
| 17 | PGEC1/AN6/OCFA/RB6 | bidirectional | PORTB I/O with programming/debugging clock channel 1, analog input 6 and Output Compare Fault A input. |
| 18 | PGED1/AN7/RB7 | bidirectional | PORTB I/O with programming/debugging data channel 1 and analog input 7. |
| 19 | AVDD | power_in | Positive supply for analog modules; must always be connected. |
| 20 | AVSS | power_in | Ground reference for analog modules; must always be connected. |
| 21 | AN8/U2CTS/RB8 | bidirectional | PORTB I/O with analog input 8 and UART2 clear-to-send. |
| 22 | AN9/RB9 | bidirectional | PORTB I/O with analog input 9. |
| 23 | TMS/AN10/RB10 | bidirectional | PORTB I/O with JTAG test mode select and analog input 10. |
| 24 | TDO/AN11/RB11 | bidirectional | PORTB I/O with JTAG test data output and analog input 11. |
| 25 | VSS | power_in | Ground reference for logic and I/O pins. |
| 26 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V). |
| 27 | TCK/AN12/RB12 | bidirectional | PORTB I/O with JTAG test clock input and analog input 12. |
| 28 | TDI/AN13/RB13 | bidirectional | PORTB I/O with JTAG test data input and analog input 13. |
| 29 | AN14/SS1/U2RTS/RB14 | bidirectional | PORTB I/O with analog input 14, SPI1 slave select and UART2 request-to-send. |
| 30 | AN15/CN12/RB15 | bidirectional | PORTB I/O with analog input 15 and change notification 12. |
| 31 | U2RX/SDA2/FLT17/CN17/RF4 | bidirectional | PORTF I/O (5V tolerant) with UART2 receive, I2C2 data, PWM Fault 17 and change notification 17. |
| 32 | U2TX/SCL2/FLT18/CN18/RF5 | bidirectional | PORTF I/O (5V tolerant) with UART2 transmit, I2C2 clock, PWM Fault 18 and change notification 18. |
| 33 | U1TX/SDO1/RF3 | bidirectional | PORTF I/O (5V tolerant) with UART1 transmit and SPI1 data out. |
| 34 | U1RX/SDI1/RF2 | bidirectional | PORTF I/O (5V tolerant) with UART1 receive and SPI1 data in. |
| 35 | U1RTS/SCK1/INT0/RF6 | bidirectional | PORTF I/O (5V tolerant) with UART1 request-to-send, SPI1 clock and external interrupt 0. |
| 36 | SDA1/RG3 | bidirectional | PORTG I/O (5V tolerant) with I2C1 serial data. |
| 37 | SCL1/RG2 | bidirectional | PORTG I/O (5V tolerant) with I2C1 serial clock. |
| 38 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V). |
| 39 | OSC1/CLKIN/RC12 | bidirectional | Oscillator crystal input or external clock input, otherwise PORTC I/O. |
| 40 | OSC2/REFCLKO/CLKO/RC15 | bidirectional | Oscillator crystal output, reference clock output or CLKO, otherwise PORTC I/O. |
| 41 | VSS | power_in | Ground reference for logic and I/O pins. |
| 42 | IC1/FLT1/SYNCI1/INT1/RD8 | bidirectional | PORTD I/O (5V tolerant) with input capture 1, PWM Fault 1, PWM sync input 1 and external interrupt 1. |
| 43 | IC2/FLT2/U1CTS/INT2/RD9 | bidirectional | PORTD I/O (5V tolerant) with input capture 2, PWM Fault 2, UART1 clear-to-send and external interrupt 2. |
| 44 | IC3/INDX1/FLT3/INT3/RD10 | bidirectional | PORTD I/O (5V tolerant) with input capture 3, QEI1 index, PWM Fault 3 and external interrupt 3. |
| 45 | IC4/QEA1/FLT4/INT4/RD11 | bidirectional | PORTD I/O (5V tolerant) with input capture 4, QEI1 phase A, PWM Fault 4 and external interrupt 4. |
| 46 | OC1/QEB1/FLT5/RD0 | bidirectional | PORTD I/O (5V tolerant) with output compare 1, QEI1 phase B and PWM Fault 5. |
| 47 | PGED2/SOSCI/T4CK/CN1/RC13 | bidirectional | PORTC I/O with programming/debugging data channel 2, 32.768 kHz secondary oscillator input, Timer4 clock and change notification 1. |
| 48 | PGEC2/SOSCO/T1CK/CN0/RC14 | bidirectional | PORTC I/O with programming/debugging clock channel 2, 32.768 kHz secondary oscillator output, Timer1 clock and change notification 0. |
| 49 | OC2/SYNCO2/FLT6/RD1 | bidirectional | PORTD I/O (5V tolerant) with output compare 2, PWM sync output 2 and PWM Fault 6. |
| 50 | OC3/FLT7/RD2 | bidirectional | PORTD I/O (5V tolerant) with output compare 3 and PWM Fault 7. |
| 51 | OC4/SYNCO1/RD3 | bidirectional | PORTD I/O (5V tolerant) with output compare 4 and PWM sync output 1. |
| 52 | PWM6L/CN13/RD4 | bidirectional | PORTD I/O (5V tolerant) with PWM6 low output and change notification 13. |
| 53 | PWM6H/CN14/RD5 | bidirectional | PORTD I/O (5V tolerant) with PWM6 high output and change notification 14. |
| 54 | PWM5L/CN15/RD6 | bidirectional | PORTD I/O (5V tolerant) with PWM5 low output and change notification 15. |
| 55 | PWM5H/UPDN1/CN16/RD7 | bidirectional | PORTD I/O (5V tolerant) with PWM5 high output, QEI1 up/down direction output and change notification 16. |
| 56 | VCAP | passive | CPU logic filter capacitor connection; requires a low-ESR (<0.5 Ohm) capacitor of at least 22 µF to ground and must not be tied to VDD. |
| 57 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V). |
| 58 | SYNCI4/RF0 | bidirectional | PORTF I/O (5V tolerant) with PWM external synchronization input 4. |
| 59 | RF1 | bidirectional | PORTF general-purpose I/O (5V tolerant). |
| 60 | PWM1L/FLT8/RE0 | bidirectional | PORTE I/O (5V tolerant) with PWM1 low output and PWM Fault 8. |
| 61 | PWM1H/RE1 | bidirectional | PORTE I/O (5V tolerant) with PWM1 high output. |
| 62 | PWM2L/RE2 | bidirectional | PORTE I/O (5V tolerant) with PWM2 low output. |
| 63 | PWM2H/RE3 | bidirectional | PORTE I/O (5V tolerant) with PWM2 high output. |
| 64 | PWM3L/RE4 | bidirectional | PORTE I/O (5V tolerant) with PWM3 low output. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-64-EP(9x9) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 65 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 3 | 3.6 | V | Industrial and extended | 371 | |
| RAM Data Retention Voltage | VDR | 1.8 | V | 371 | |||
| VDD Rise Rate | SVDD | 0.03 | V/ms | 0-3.0V in 0.1s | 371 | ||
| Max MIPS | 40 | MIPS | 3.0-3.6V, -40C to +85C | 370 | |||
| Operating Ambient Temperature Range (Industrial) | TA | -40 | 85 | °C | Industrial temperature devices | 370 | |
| Operating Junction Temperature Range (Industrial) | TJ | -40 | 125 | °C | Industrial temperature devices | 370 | |
| Ambient temperature under bias | -40 | 125 | °C | 369 | |||
| Storage temperature | -65 | 150 | °C | 369 | |||
| Voltage on VDD with respect to VSS | VDD | -0.3 | 4 | V | 369 | ||
| Voltage on any 5V tolerant pin with respect to VSS | -0.3 | 5.6 | V | when VDD ≥ 3.0V | 369 | ||
| Operating Current (IDD) DC24d | IDD | 66 | 75 | mA | -40°C, 3.3V 40 MIPS (See Note 2) | 372 | |
| Operating Current (IDD) DC24a | IDD | 66 | 75 | mA | +25°C, 3.3V 40 MIPS (See Note 2) | 372 | |
| Operating Current (IDD) DC24b | IDD | 66 | 75 | mA | +85°C, 3.3V 40 MIPS (See Note 2) | 372 | |
| Operating Current (IDD) DC24c | IDD | 67 | 75 | mA | +125°C, 3.3V 40 MIPS (See Note 2) | 372 | |
| Operating Current (IDD) DC25d | IDD | 153 | 170 | mA | -40°C, 3.3V 40 MIPS (See Notes 2 and 3), except PWM is operating at maximum speed (PTCON2 = 0x0000) | 372 | |
| Operating Current (IDD) DC25a | IDD | 154 | 170 | mA | +25°C, 3.3V 40 MIPS (See Notes 2 and 3), except PWM is operating at maximum speed (PTCON2 = 0x0000) | 372 | |
| Operating Current (IDD) DC25b | IDD | 155 | 170 | mA | +85°C, 3.3V 40 MIPS (See Notes 2 and 3), except PWM is operating at maximum speed (PTCON2 = 0x0000) | 372 | |
| Idle Current (IIDLE) DC44d | IIDLE | 29 | 40 | mA | -40°C, 3.3V 40 MIPS | 374 | |
| Idle Current (IIDLE) DC44a | IIDLE | 29 | 40 | mA | +25°C, 3.3V 40 MIPS | 374 | |
| Idle Current (IIDLE) DC44b | IIDLE | 30 | 40 | mA | +85°C, 3.3V 40 MIPS | 374 | |
| Idle Current (IIDLE) DC44c | IIDLE | 31 | 40 | mA | +125°C, 3.3V 40 MIPS | 374 | |
| Power-Down Current (IPD) DC60d | IPD | 50 | 500 | µA | -40°C, 3.3V Base Power-Down Current | 375 | |
| Power-Down Current (IPD) DC60a | IPD | 50 | 500 | µA | +25°C, 3.3V Base Power-Down Current | 375 | |
| Power-Down Current (IPD) DC60b | IPD | 200 | 500 | µA | +85°C, 3.3V Base Power-Down Current | 375 | |
| Power-Down Current (IPD) DC60c | IPD | 600 | 1000 | µA | +125°C, 3.3V Base Power-Down Current | 375 | |
| Watchdog Timer Current DC61d | IWDT | 8 | 13 | µA | -40°C, 3.3V Watchdog Timer Current: IWDT | 375 | |
| Watchdog Timer Current DC61a | IWDT | 10 | 15 | µA | +25°C, 3.3V Watchdog Timer Current: IWDT | 375 | |
| Watchdog Timer Current DC61b | IWDT | 12 | 20 | µA | +85°C, 3.3V Watchdog Timer Current: IWDT | 375 | |
| Watchdog Timer Current DC61c | IWDT | 13 | 25 | µA | +125°C, 3.3V Watchdog Timer Current: IWDT | 375 | |
| Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm) | JA | 28 | °C/W | 370 |
CAD (KiCad official)
- Symbol:
dsPIC33FJ64GS406-I - Footprint:
Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm - 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files:
dspic33fj64gs406-i-etched.step/dspic33fj64gs406-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dspic33fj64gs406-i.step/dspic33fj64gs406-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (462 pp, sha256
5ca79959afa012d4, retrieved 2026-11-09, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# dsPIC33FJ64GS406-I
**Microchip Tech** · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-64-EP(9x9)
dsPIC33FJ64GS406-I from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PWM3H/RE5 | bidirectional | PORTE I/O shared with PWM3 high output. |
| 2 | PWM4L/RE6 | bidirectional | PORTE I/O shared with PWM4 low output. |
| 3 | PWM4H/RE7 | bidirectional | PORTE I/O shared with PWM4 high output. |
| 4 | SCK2/FLT12/CN8/RG6 | bidirectional | PORTG I/O with SPI2 serial clock, PWM Fault 12 input and change notification 8. |
| 5 | SDI2/FLT11/CN9/RG7 | bidirectional | PORTG I/O with SPI2 data in, PWM Fault 11 input and change notification 9. |
| 6 | SDO2/FLT10/CN10/RG8 | bidirectional | PORTG I/O with SPI2 data out, PWM Fault 10 input and change notification 10. |
| 7 | MCLR | input | Master Clear active-low Reset input to the device, also used for programming and debugging. |
| 8 | SS2/FLT9/SYNCI2/CN11/RG9 | bidirectional | PORTG I/O with SPI2 slave select, PWM Fault 9, PWM external synchronization input 2 and change notification 11. |
| 9 | VSS | power_in | Ground reference for logic and I/O pins. |
| 10 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V). |
| 11 | AN5/AQEB1/CN7/RB5 | bidirectional | PORTB I/O with analog input 5, alternate QEI1 phase B input and change notification 7. |
| 12 | AN4/AQEA1/CN6/RB4 | bidirectional | PORTB I/O with analog input 4, alternate QEI1 phase A input and change notification 6. |
| 13 | AN3/AINDX1/CN5/RB3 | bidirectional | PORTB I/O with analog input 3, alternate QEI1 index input and change notification 5. |
| 14 | AN2/ASS1/CN4/RB2 | bidirectional | PORTB I/O with analog input 2, alternate SPI1 slave select and change notification 4. |
| 15 | PGEC3/AN1/CN3/RB1 | bidirectional | PORTB I/O with analog input 1, programming/debugging clock channel 3 and change notification 3. |
| 16 | PGED3/AN0/CN2/RB0 | bidirectional | PORTB I/O with analog input 0, programming/debugging data channel 3 and change notification 2. |
| 17 | PGEC1/AN6/OCFA/RB6 | bidirectional | PORTB I/O with programming/debugging clock channel 1, analog input 6 and Output Compare Fault A input. |
| 18 | PGED1/AN7/RB7 | bidirectional | PORTB I/O with programming/debugging data channel 1 and analog input 7. |
| 19 | AVDD | power_in | Positive supply for analog modules; must always be connected. |
| 20 | AVSS | power_in | Ground reference for analog modules; must always be connected. |
| 21 | AN8/U2CTS/RB8 | bidirectional | PORTB I/O with analog input 8 and UART2 clear-to-send. |
| 22 | AN9/RB9 | bidirectional | PORTB I/O with analog input 9. |
| 23 | TMS/AN10/RB10 | bidirectional | PORTB I/O with JTAG test mode select and analog input 10. |
| 24 | TDO/AN11/RB11 | bidirectional | PORTB I/O with JTAG test data output and analog input 11. |
| 25 | VSS | power_in | Ground reference for logic and I/O pins. |
| 26 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V). |
| 27 | TCK/AN12/RB12 | bidirectional | PORTB I/O with JTAG test clock input and analog input 12. |
| 28 | TDI/AN13/RB13 | bidirectional | PORTB I/O with JTAG test data input and analog input 13. |
| 29 | AN14/SS1/U2RTS/RB14 | bidirectional | PORTB I/O with analog input 14, SPI1 slave select and UART2 request-to-send. |
| 30 | AN15/CN12/RB15 | bidirectional | PORTB I/O with analog input 15 and change notification 12. |
| 31 | U2RX/SDA2/FLT17/CN17/RF4 | bidirectional | PORTF I/O (5V tolerant) with UART2 receive, I2C2 data, PWM Fault 17 and change notification 17. |
| 32 | U2TX/SCL2/FLT18/CN18/RF5 | bidirectional | PORTF I/O (5V tolerant) with UART2 transmit, I2C2 clock, PWM Fault 18 and change notification 18. |
| 33 | U1TX/SDO1/RF3 | bidirectional | PORTF I/O (5V tolerant) with UART1 transmit and SPI1 data out. |
| 34 | U1RX/SDI1/RF2 | bidirectional | PORTF I/O (5V tolerant) with UART1 receive and SPI1 data in. |
| 35 | U1RTS/SCK1/INT0/RF6 | bidirectional | PORTF I/O (5V tolerant) with UART1 request-to-send, SPI1 clock and external interrupt 0. |
| 36 | SDA1/RG3 | bidirectional | PORTG I/O (5V tolerant) with I2C1 serial data. |
| 37 | SCL1/RG2 | bidirectional | PORTG I/O (5V tolerant) with I2C1 serial clock. |
| 38 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V). |
| 39 | OSC1/CLKIN/RC12 | bidirectional | Oscillator crystal input or external clock input, otherwise PORTC I/O. |
| 40 | OSC2/REFCLKO/CLKO/RC15 | bidirectional | Oscillator crystal output, reference clock output or CLKO, otherwise PORTC I/O. |
| 41 | VSS | power_in | Ground reference for logic and I/O pins. |
| 42 | IC1/FLT1/SYNCI1/INT1/RD8 | bidirectional | PORTD I/O (5V tolerant) with input capture 1, PWM Fault 1, PWM sync input 1 and external interrupt 1. |
| 43 | IC2/FLT2/U1CTS/INT2/RD9 | bidirectional | PORTD I/O (5V tolerant) with input capture 2, PWM Fault 2, UART1 clear-to-send and external interrupt 2. |
| 44 | IC3/INDX1/FLT3/INT3/RD10 | bidirectional | PORTD I/O (5V tolerant) with input capture 3, QEI1 index, PWM Fault 3 and external interrupt 3. |
| 45 | IC4/QEA1/FLT4/INT4/RD11 | bidirectional | PORTD I/O (5V tolerant) with input capture 4, QEI1 phase A, PWM Fault 4 and external interrupt 4. |
| 46 | OC1/QEB1/FLT5/RD0 | bidirectional | PORTD I/O (5V tolerant) with output compare 1, QEI1 phase B and PWM Fault 5. |
| 47 | PGED2/SOSCI/T4CK/CN1/RC13 | bidirectional | PORTC I/O with programming/debugging data channel 2, 32.768 kHz secondary oscillator input, Timer4 clock and change notification 1. |
| 48 | PGEC2/SOSCO/T1CK/CN0/RC14 | bidirectional | PORTC I/O with programming/debugging clock channel 2, 32.768 kHz secondary oscillator output, Timer1 clock and change notification 0. |
| 49 | OC2/SYNCO2/FLT6/RD1 | bidirectional | PORTD I/O (5V tolerant) with output compare 2, PWM sync output 2 and PWM Fault 6. |
| 50 | OC3/FLT7/RD2 | bidirectional | PORTD I/O (5V tolerant) with output compare 3 and PWM Fault 7. |
| 51 | OC4/SYNCO1/RD3 | bidirectional | PORTD I/O (5V tolerant) with output compare 4 and PWM sync output 1. |
| 52 | PWM6L/CN13/RD4 | bidirectional | PORTD I/O (5V tolerant) with PWM6 low output and change notification 13. |
| 53 | PWM6H/CN14/RD5 | bidirectional | PORTD I/O (5V tolerant) with PWM6 high output and change notification 14. |
| 54 | PWM5L/CN15/RD6 | bidirectional | PORTD I/O (5V tolerant) with PWM5 low output and change notification 15. |
| 55 | PWM5H/UPDN1/CN16/RD7 | bidirectional | PORTD I/O (5V tolerant) with PWM5 high output, QEI1 up/down direction output and change notification 16. |
| 56 | VCAP | passive | CPU logic filter capacitor connection; requires a low-ESR (<0.5 Ohm) capacitor of at least 22 µF to ground and must not be tied to VDD. |
| 57 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V). |
| 58 | SYNCI4/RF0 | bidirectional | PORTF I/O (5V tolerant) with PWM external synchronization input 4. |
| 59 | RF1 | bidirectional | PORTF general-purpose I/O (5V tolerant). |
| 60 | PWM1L/FLT8/RE0 | bidirectional | PORTE I/O (5V tolerant) with PWM1 low output and PWM Fault 8. |
| 61 | PWM1H/RE1 | bidirectional | PORTE I/O (5V tolerant) with PWM1 high output. |
| 62 | PWM2L/RE2 | bidirectional | PORTE I/O (5V tolerant) with PWM2 low output. |
| 63 | PWM2H/RE3 | bidirectional | PORTE I/O (5V tolerant) with PWM2 high output. |
| 64 | PWM3L/RE4 | bidirectional | PORTE I/O (5V tolerant) with PWM3 low output. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-64-EP(9x9) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 65 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 3 | | 3.6 | V | Industrial and extended | 371 |
| RAM Data Retention Voltage | VDR | 1.8 | | | V | | 371 |
| VDD Rise Rate | SVDD | 0.03 | | | V/ms | 0-3.0V in 0.1s | 371 |
| Max MIPS | | | | 40 | MIPS | 3.0-3.6V, -40C to +85C | 370 |
| Operating Ambient Temperature Range (Industrial) | TA | -40 | | 85 | °C | Industrial temperature devices | 370 |
| Operating Junction Temperature Range (Industrial) | TJ | -40 | | 125 | °C | Industrial temperature devices | 370 |
| Ambient temperature under bias | | -40 | | 125 | °C | | 369 |
| Storage temperature | | -65 | | 150 | °C | | 369 |
| Voltage on VDD with respect to VSS | VDD | -0.3 | | 4 | V | | 369 |
| Voltage on any 5V tolerant pin with respect to VSS | | -0.3 | | 5.6 | V | when VDD ≥ 3.0V | 369 |
| Operating Current (IDD) DC24d | IDD | | 66 | 75 | mA | -40°C, 3.3V 40 MIPS (See Note 2) | 372 |
| Operating Current (IDD) DC24a | IDD | | 66 | 75 | mA | +25°C, 3.3V 40 MIPS (See Note 2) | 372 |
| Operating Current (IDD) DC24b | IDD | | 66 | 75 | mA | +85°C, 3.3V 40 MIPS (See Note 2) | 372 |
| Operating Current (IDD) DC24c | IDD | | 67 | 75 | mA | +125°C, 3.3V 40 MIPS (See Note 2) | 372 |
| Operating Current (IDD) DC25d | IDD | | 153 | 170 | mA | -40°C, 3.3V 40 MIPS (See Notes 2 and 3), except PWM is operating at maximum speed (PTCON2 = 0x0000) | 372 |
| Operating Current (IDD) DC25a | IDD | | 154 | 170 | mA | +25°C, 3.3V 40 MIPS (See Notes 2 and 3), except PWM is operating at maximum speed (PTCON2 = 0x0000) | 372 |
| Operating Current (IDD) DC25b | IDD | | 155 | 170 | mA | +85°C, 3.3V 40 MIPS (See Notes 2 and 3), except PWM is operating at maximum speed (PTCON2 = 0x0000) | 372 |
| Idle Current (IIDLE) DC44d | IIDLE | | 29 | 40 | mA | -40°C, 3.3V 40 MIPS | 374 |
| Idle Current (IIDLE) DC44a | IIDLE | | 29 | 40 | mA | +25°C, 3.3V 40 MIPS | 374 |
| Idle Current (IIDLE) DC44b | IIDLE | | 30 | 40 | mA | +85°C, 3.3V 40 MIPS | 374 |
| Idle Current (IIDLE) DC44c | IIDLE | | 31 | 40 | mA | +125°C, 3.3V 40 MIPS | 374 |
| Power-Down Current (IPD) DC60d | IPD | | 50 | 500 | µA | -40°C, 3.3V Base Power-Down Current | 375 |
| Power-Down Current (IPD) DC60a | IPD | | 50 | 500 | µA | +25°C, 3.3V Base Power-Down Current | 375 |
| Power-Down Current (IPD) DC60b | IPD | | 200 | 500 | µA | +85°C, 3.3V Base Power-Down Current | 375 |
| Power-Down Current (IPD) DC60c | IPD | | 600 | 1000 | µA | +125°C, 3.3V Base Power-Down Current | 375 |
| Watchdog Timer Current DC61d | IWDT | | 8 | 13 | µA | -40°C, 3.3V Watchdog Timer Current: IWDT | 375 |
| Watchdog Timer Current DC61a | IWDT | | 10 | 15 | µA | +25°C, 3.3V Watchdog Timer Current: IWDT | 375 |
| Watchdog Timer Current DC61b | IWDT | | 12 | 20 | µA | +85°C, 3.3V Watchdog Timer Current: IWDT | 375 |
| Watchdog Timer Current DC61c | IWDT | | 13 | 25 | µA | +125°C, 3.3V Watchdog Timer Current: IWDT | 375 |
| Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm) | JA | | 28 | | °C/W | | 370 |
## CAD (KiCad official)
- Symbol: `dsPIC33FJ64GS406-I`
- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`
- 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files: `dspic33fj64gs406-i-etched.step` / `dspic33fj64gs406-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dspic33fj64gs406-i.step` / `dspic33fj64gs406-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/dspic33fj64gs406-i-datasheet.pdf) (462 pp, sha256 `5ca79959afa012d4`, retrieved 2026-11-09, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dspic33fj64gs406-i-datasheet.pdf)