component

dsPIC33FJ64GP802-E

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollerdspic33fj64gp802-efactory-2.0.0extractor-text

Changed since verified dsPIC33FJ64GP802-E

by Ray · last 30 Oct 2026 · 1 record · files changed since
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 28 pinschanged since
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: dsPIC33FJ64GP802-E · SOIC-28-300mil · 28 pins
  • ✓copper: 28 copper pads, none touching another net
  • ✓datasheet: all 28 pin names found in the 436-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-28W_7.5x17.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-1jnthxuh/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 28 pins = 28 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 28 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! dspic33fj64gp802-e.kicad_sym✓ dspic33fj64gp802-e.kicad_mod✓ dspic33fj64gp802-e.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers dspic33fj64gp802-e: symbol repaired (body fitted to the names) · Ray
dspic33fj64gp802-e-etched.glb Publish 0.1.0 · Ray
dspic33fj64gp802-e-etched.step dspic33fj64gp802-e: factory component page (tier=mfr) · Ray
dspic33fj64gp802-e-hero.glb dspic33fj64gp802-e: hero GLB from the etched model (keeps the MPN mark) · Ray
dspic33fj64gp802-e-hero.overlay.json Publish 0.1.0 · Ray
dspic33fj64gp802-e.glb Publish 0.1.0 · Ray
dspic33fj64gp802-e.kicad_mod Publish 0.1.0 · Ray
dspic33fj64gp802-e.kicad_sym dspic33fj64gp802-e: symbol repaired (body fitted to the names) · Ray
dspic33fj64gp802-e.lbr dspic33fj64gp802-e: symbol repaired (body fitted to the names) · Ray
dspic33fj64gp802-e.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 28 pins · Ray

dsPIC33FJ64GP802-E

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · SOIC-28-300mil

dsPIC33FJ64GP802-E from Microchip Tech, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MCLR input Master Clear active-low Reset input that also serves device programming and debugging.
2 AN0/VREF+/CN2/RA0 bidirectional Analog input AN0 and ADC positive voltage reference input VREF+, with change notification CN2 and PORTA bit RA0.
3 AN1/VREF-/CN3/RA1 bidirectional Analog input AN1 and ADC negative voltage reference input VREF-, with change notification CN3 and PORTA bit RA1.
4 PGED1/AN2/C2IN-/RP0/CN4/RB0 bidirectional ICSP data pin PGED1, analog input AN2, comparator 2 negative input, remappable pin RP0, CN4 and PORTB bit RB0.
5 PGEC1/AN3/C2IN+/RP1/CN5/RB1 bidirectional ICSP clock pin PGEC1, analog input AN3, comparator 2 positive input, remappable pin RP1, CN5 and PORTB bit RB1.
6 AN4/C1IN-/RP2/CN6/RB2 bidirectional Analog input AN4, comparator 1 negative input, remappable pin RP2, CN6 and PORTB bit RB2.
7 AN5/C1IN+/RP3/CN7/RB3 bidirectional Analog input AN5, comparator 1 positive input, remappable pin RP3, CN7 and PORTB bit RB3.
8 VSS power_in Ground reference for logic and I/O pins; must always be connected.
9 OSC1/CLKI/CN30/RA2 bidirectional Oscillator crystal input or external clock input CLKI, with CN30 and PORTA bit RA2.
10 OSC2/CLKO/CN29/PMA0/RA3 bidirectional Oscillator crystal output or CLKO in RC and EC modes, with CN29, PMP address bit PMA0 and PORTA bit RA3.
11 SOSCI/RP4/CN1/PMBE/RB4 bidirectional 32.768 kHz secondary oscillator crystal input, remappable pin RP4, CN1, PMP byte enable PMBE and PORTB bit RB4.
12 SOSCO/T1CK/CN0/PMA1/RA4 bidirectional 32.768 kHz secondary oscillator crystal output, Timer1 external clock input T1CK, CN0, PMP address bit PMA1 and PORTA bit RA4.
13 VDD power_in Positive supply for peripheral logic and I/O pins, 3.0V to 3.6V operating range.
14 PGED3/ASDA1/RP5/CN27/PMD7/RB5 bidirectional ICSP data pin PGED3, alternate I2C1 data ASDA1, remappable pin RP5, CN27, PMP data PMD7 and PORTB bit RB5.
15 PGEC3/ASCL1/RP6/CN24/PMD6/RB6 bidirectional ICSP clock pin PGEC3, alternate I2C1 clock ASCL1, remappable pin RP6, CN24, PMP data PMD6 and PORTB bit RB6.
16 INT0/RP7/CN23/PMD5/RB7 bidirectional External interrupt 0, remappable pin RP7, CN23, PMP data PMD5 and PORTB bit RB7.
17 TCK/SCL1/RP8/CN22/PMD4/RB8 bidirectional JTAG test clock TCK, I2C1 clock SCL1, remappable pin RP8, CN22, PMP data PMD4 and PORTB bit RB8.
18 TDO/SDA1/RP9/CN21/PMD3/RB9 bidirectional JTAG test data output TDO, I2C1 data SDA1, remappable pin RP9, CN21, PMP data PMD3 and PORTB bit RB9.
19 VSS power_in Ground reference for logic and I/O pins; must always be connected.
20 VCAP passive CPU logic filter capacitor connection; needs a low-ESR (<5 Ohm) 4.7 uF to 10 uF capacitor to ground and must not be connected to VDD.
21 PGED2/TDI/RP10/CN16/PMD2/RB10 bidirectional ICSP data pin PGED2, JTAG test data input TDI, remappable pin RP10, CN16, PMP data PMD2 and PORTB bit RB10.
22 PGEC2/TMS/RP11/CN15/PMD1/RB11 bidirectional ICSP clock pin PGEC2, JTAG test mode select TMS, remappable pin RP11, CN15, PMP data PMD1 and PORTB bit RB11.
23 AN12/DAC1RP/RP12/CN14/PMD0/RB12 bidirectional Analog input AN12, DAC1 right channel positive output, remappable pin RP12, CN14, PMP data PMD0 and PORTB bit RB12.
24 AN11/DAC1RN/RP13/CN13/PMRD/RB13 bidirectional Analog input AN11, DAC1 right channel negative output, remappable pin RP13, CN13, PMP read strobe PMRD and PORTB bit RB13.
25 AN10/DAC1LP/RTCC/RP14/CN12/PMWR/RB14 bidirectional Analog input AN10, DAC1 left channel positive output, RTCC alarm output, remappable pin RP14, CN12, PMP write strobe PMWR and PORTB bit RB14.
26 AN9/DAC1LN/RP15/CN11/PMCS1/RB15 bidirectional Analog input AN9, DAC1 left channel negative output, remappable pin RP15, CN11, PMP chip select PMCS1 and PORTB bit RB15.
27 AVSS power_in Ground reference for analog modules; must always be connected.
28 AVDD power_in Positive supply for analog modules; must be connected at all times.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-28-300mil
Category Single Chip Microcomputer/Microcontroller
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD (operating, -40ºC to +125ºC, DC to 40 MIPS) VDD 3 3.6 V -40ºC to +125ºC, DC to 40 MIPS 1
Supply voltage VDD (operating, -40ºC to +150ºC, DC to 20 MIPS) VDD 3 3.6 V -40ºC to +150ºC, DC to 20 MIPS 1
Operating temperature (DC to 40 MIPS) -40 125 ºC 3.0V to 3.6V, DC to 40 MIPS 1
Operating temperature (DC to 20 MIPS) -40 150 ºC 3.0V to 3.6V, DC to 20 MIPS 1
Maximum CPU speed (-40ºC to +125ºC) 40 MIPS 3.0V to 3.6V, -40ºC to +125ºC 1
Maximum CPU speed (-40ºC to +150ºC) 20 MIPS 3.0V to 3.6V, -40ºC to +150ºC 1
Overvoltage clamp current per pin 5 mA Per pin, as stated in the features list 1
POR threshold VPOR 1.8 V Nominal 83
POR extension time TPOR 30 μs Maximum 83
BOR threshold VBOR 2.5 V Nominal 83
BOR extension time TBOR 100 μs Maximum 83
Programmable power-up time delay TPWRT 0 128 ms Nominal, selected by FPWRT<2:0> 83
Fail-Safe Clock Monitor delay TFSCM 900 μs Maximum 83
Oscillator start-up delay (FRC) TOSCD 1.1 μs Maximum, FRC 81
Oscillator start-up delay (LPRC) TOSCD 70 μs Maximum, LPRC 81
PLL lock time TLOCK 1.5 ms Nominal, if PLL is enabled 81
Maximum oscillator source frequency for start-up with PLL enabled 8 MHz PLL enabled at device start-up 22
VCAP pin voltage VCAP 2.5 V Typical, when VDD ≥ VDDMIN 319
VCAP filter capacitor 4.7 10 µF Low-ESR capacitor on VCAP pin, ceramic or tantalum 20
VCAP capacitor ESR 5 Ohms Low-ESR capacitor on VCAP pin, less than 5 Ohms 20
VDD/VSS decoupling capacitor value 0.1 µF Recommended ceramic, low-ESR, on every VDD/VSS and AVDD/AVSS pair 19
VDD/VSS decoupling capacitor voltage rating 10 20 V Recommended 0.1 µF ceramic, 10-20V 19
MCLR series resistor R 10 10 kΩ Recommended R ≤ 10 kΩ; suggested starting value 10 kΩ 20
MCLR current-limit resistor R1 470 Ω R1 ≤ 470Ω limits current into MCLR in the event of ESD/EOS breakdown 20

CAD (KiCad official)

  • Symbol: dsPIC33FJ64GP802-E
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
  • 3D model files: dspic33fj64gp802-e-etched.step / dspic33fj64gp802-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dspic33fj64gp802-e.step / dspic33fj64gp802-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (436 pp, sha256 7e540c84de50041b, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF