component
dsPIC33FJ32MC202-E
Public Made by Adomby adom
Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdowndsPIC33FJ32MC202-E
Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · SOIC-28-300mil
dsPIC33FJ32MC202-E from Microchip Tech, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MCLR | input | Active-low Master Clear (Reset) input, 5V tolerant, also used for device programming and debugging. |
| 2 | AN0/VREF+/CN2/RA0 | bidirectional | Analog input 0 / positive ADC voltage reference input / change notification 2 / PORTA bit 0. |
| 3 | AN1/VREF-/CN3/RA1 | bidirectional | Analog input 1 / negative ADC voltage reference input / change notification 3 / PORTA bit 1. |
| 4 | PGED1/AN2/C2IN-/RP0/CN4/RB0 | bidirectional | Programming/debug data I/O channel 1, analog input 2, comparator 2 input-, remappable pin RP0, change notification 4, PORTB bit 0. |
| 5 | PGEC1/AN3/C2IN+/RP1/CN5/RB1 | bidirectional | Programming/debug clock channel 1, analog input 3, comparator 2 input+, remappable pin RP1, change notification 5, PORTB bit 1. |
| 6 | AN4/RP2/CN6/RB2 | bidirectional | Analog input 4, remappable pin RP2, change notification 6, PORTB bit 2. |
| 7 | AN5/RP3/CN7/RB3 | bidirectional | Analog input 5, remappable pin RP3, change notification 7, PORTB bit 3. |
| 8 | VSS | power_in | Ground reference for logic and I/O pins. |
| 9 | OSC1/CLKI/CN30/RA2 | bidirectional | Oscillator crystal input or external clock input (ST buffer in RC mode, CMOS otherwise), change notification 30, PORTA bit 2. |
| 10 | OSC2/CLKO/CN29/RA3 | bidirectional | Oscillator crystal output or CLKO in RC and EC modes, change notification 29, PORTA bit 3 (8x drive pin). |
| 11 | SOSCI/RP4/CN1/RB4 | bidirectional | 32.768 kHz secondary oscillator crystal input, remappable pin RP4, change notification 1, PORTB bit 4. |
| 12 | SOSCO/T1CK/CN0/RA4 | bidirectional | 32.768 kHz secondary oscillator crystal output, Timer1 external clock input, change notification 0, PORTA bit 4. |
| 13 | VDD | power_in | Positive supply for peripheral logic and I/O pins. |
| 14 | PGED3/ASDA1/RP5/CN27/RB5 | bidirectional | Programming/debug data I/O channel 3, alternate I2C1 data, remappable pin RP5, change notification 27, PORTB bit 5; 5V tolerant. |
| 15 | PGEC3/ASCL1/RP6/CN24/RB6 | bidirectional | Programming/debug clock channel 3, alternate I2C1 clock, remappable pin RP6, change notification 24, PORTB bit 6; 5V tolerant. |
| 16 | INT0/RP7/CN23/RB7 | bidirectional | External interrupt 0, remappable pin RP7, change notification 23, PORTB bit 7; 5V tolerant. |
| 17 | TCK/PWM2H1/SCL1/RP8/CN22/RB8 | bidirectional | JTAG test clock input, PWM2 high output 1, I2C1 clock, remappable pin RP8, change notification 22, PORTB bit 8; 5V tolerant. |
| 18 | TDO/PWM2L1/SDA1/RP9/CN21/RB9 | bidirectional | JTAG test data output, PWM2 low output 1, I2C1 data, remappable pin RP9, change notification 21, PORTB bit 9; 5V tolerant. |
| 19 | VSS | power_in | Ground reference for logic and I/O pins. |
| 20 | VCAP | passive | CPU logic filter capacitor connection; needs a low-ESR (<5 Ohm) 4.7-10 uF capacitor to ground and must not be connected to VDD. |
| 21 | PGED2/TDI/PWM1H3/RP10/CN16/RB10 | bidirectional | Programming/debug data I/O channel 2, JTAG test data input, PWM1 high output 3, remappable pin RP10, change notification 16, PORTB bit 10; 5V tolerant. |
| 22 | PGEC2/TMS/PWM1L3/RP11/CN15/RB11 | bidirectional | Programming/debug clock channel 2, JTAG test mode select, PWM1 low output 3, remappable pin RP11, change notification 15, PORTB bit 11; 5V tolerant. |
| 23 | PWM1H2/RP12/CN14/RB12 | bidirectional | PWM1 high output 2, remappable pin RP12, change notification 14, PORTB bit 12. |
| 24 | PWM1L2/RP13/CN13/RB13 | bidirectional | PWM1 low output 2, remappable pin RP13, change notification 13, PORTB bit 13. |
| 25 | PWM1H1/RP14/CN12/RB14 | bidirectional | PWM1 high output 1, remappable pin RP14, change notification 12, PORTB bit 14. |
| 26 | PWM1L1/RP15/CN11/RB15 | bidirectional | PWM1 low output 1, remappable pin RP15, change notification 11, PORTB bit 15. |
| 27 | AVSS | power_in | Ground reference for analog modules; must always be connected. |
| 28 | AVDD | power_in | Positive supply for analog modules; must be connected at all times. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-28-300mil |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 3 | 3.6 | V | Operating Conditions bullet, paired with -40ºC to +125ºC, DC to 40 MIPS | 1 | |
| Operating temperature | -40 | 125 | ºC | DC to 40 MIPS, 3.0V to 3.6V | 1 | ||
| Operating temperature | -40 | 150 | ºC | DC to 20 MIPS, 3.0V to 3.6V | 1 | ||
| VCAP external filter capacitor | CEFC | 4.7 | 10 | µF | Connected from VCAP to ground; ceramic or tantalum; 16V rated as printed | 14 | |
| VCAP capacitor ESR | 5 | Ohms | Low-ESR capacitor on VCAP, printed as less than 5 Ohms | 14 | |||
| Overvoltage clamp current | 5 | mA | Up to 5 mA overvoltage clamp current, feature list | 1 | |||
| Sink/source current, standard VOH/VOL | 10 | mA | Pin specific, standard VOH/VOL, feature list | 1 | |||
| Sink/source current, non-standard VOH1 | VOH1 | 16 | mA | Pin specific, non-standard VOH1, feature list | 1 | ||
| POR extension time | TPOR | 30 | µs | 67 | |||
| BOR extension time | TBOR | 100 | µs | 67 | |||
| Fail-Safe Clock Monitor delay | TFSCM | 900 | µs | 67 | |||
| Oscillator start-up delay, FRC | TOSCD | 1.1 | µs | FRC oscillator, Table 6-1 note 1 | 65 | ||
| Oscillator start-up delay, LPRC | TOSCD | 70 | µs | LPRC oscillator, Table 6-1 note 1 | 65 | ||
| Programmable power-up time delay | TPWRT | 0 | 128 | ms | Nominal, set by FPWRT<2:0> | 67 | |
| POR threshold | VPOR | 1.8 | V | Nominal | 67 | ||
| BOR threshold | VBOR | 2.5 | V | Nominal | 67 | ||
| PLL lock time | TLOCK | 1.5 | ms | Nominal, if PLL is enabled | 65 | ||
| On-chip regulator start-up time | TSTARTUP | 20 | µs | On a POR, approximately | 215 |
CAD (KiCad official)
- Symbol:
dsPIC33FJ32MC202-E - Footprint:
Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm - 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
- 3D model files:
dspic33fj32mc202-e-etched.step/dspic33fj32mc202-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dspic33fj32mc202-e.step/dspic33fj32mc202-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (330 pp, sha256
facbf201cb5935c3, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).