component
dsPIC33FJ128GP802-E
Public Made by Adomby adom
Microchip Tech Digital Signal Processors / Controllers (DSPs/DSCs), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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Datasheet
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README
markdowndsPIC33FJ128GP802-E
Microchip Tech · Digital Signal Processors / Controllers (DSPs/DSCs) · SOIC-28-300mil
dsPIC33FJ128GP802-E from Microchip Tech, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MCLR | input | Master Clear (active-low Reset) input, also used for device programming and debugging. |
| 2 | AN0/VREF+/CN2/RA0 | bidirectional | Analog input 0 and ADC positive voltage reference input, with change notification 2 and PORTA bit 0 I/O. |
| 3 | AN1/VREF-/CN3/RA1 | bidirectional | Analog input 1 and ADC negative voltage reference input, with change notification 3 and PORTA bit 1 I/O. |
| 4 | PGED1/AN2/C2IN-/RP0/CN4/RB0 | bidirectional | Programming/debugging data I/O channel 1, analog input 2, Comparator 2 negative input, remappable RP0 and PORTB bit 0. |
| 5 | PGEC1/AN3/C2IN+/RP1/CN5/RB1 | bidirectional | Programming/debugging clock channel 1, analog input 3, Comparator 2 positive input, remappable RP1 and PORTB bit 1. |
| 6 | AN4/C1IN-/RP2/CN6/RB2 | bidirectional | Analog input 4, Comparator 1 negative input, remappable RP2 and PORTB bit 2. |
| 7 | AN5/C1IN+/RP3/CN7/RB3 | bidirectional | Analog input 5, Comparator 1 positive input, remappable RP3 and PORTB bit 3. |
| 8 | VSS | power_in | Ground reference for logic and I/O pins. |
| 9 | OSC1/CLKI/CN30/RA2 | bidirectional | Oscillator crystal input or external clock input, with change notification 30 and PORTA bit 2. |
| 10 | OSC2/CLKO/CN29/PMA0/RA3 | bidirectional | Oscillator crystal output or CLKO, with PMP address bit 0, change notification 29 and PORTA bit 3. |
| 11 | SOSCI/RP4/CN1/PMBE/RB4 | bidirectional | 32.768 kHz secondary oscillator crystal input, remappable RP4, PMP byte enable strobe and PORTB bit 4. |
| 12 | SOSCO/T1CK/CN0/PMA1/RA4 | bidirectional | 32.768 kHz secondary oscillator crystal output, Timer1 external clock input, PMP address bit 1 and PORTA bit 4. |
| 13 | VDD | power_in | Positive supply for peripheral logic and I/O pins. |
| 14 | PGED3/ASDA1/RP5/CN27/PMD7/RB5 | bidirectional | Programming/debugging data I/O channel 3, alternate I2C1 data, remappable RP5, PMP data bit 7 and PORTB bit 5. |
| 15 | PGEC3/ASCL1/RP6/CN24/PMD6/RB6 | bidirectional | Programming/debugging clock channel 3, alternate I2C1 clock, remappable RP6, PMP data bit 6 and PORTB bit 6. |
| 16 | INT0/RP7/CN23/PMD5/RB7 | bidirectional | External interrupt 0, remappable RP7, PMP data bit 5 and PORTB bit 7. |
| 17 | TCK/SCL1/RP8/CN22/PMD4/RB8 | bidirectional | JTAG test clock input, I2C1 clock, remappable RP8, PMP data bit 4 and PORTB bit 8. |
| 18 | TDO/SDA1/RP9/CN21/PMD3/RB9 | bidirectional | JTAG test data output, I2C1 data, remappable RP9, PMP data bit 3 and PORTB bit 9. |
| 19 | VSS | power_in | Ground reference for logic and I/O pins. |
| 20 | VCAP | passive | CPU logic filter capacitor connection; needs a low-ESR (<5 Ohm) 4.7 uF to 10 uF capacitor to ground and must not be connected to VDD. |
| 21 | PGED2/TDI/RP10/CN16/PMD2/RB10 | bidirectional | Programming/debugging data I/O channel 2, JTAG test data input, remappable RP10, PMP data bit 2 and PORTB bit 10. |
| 22 | PGEC2/TMS/RP11/CN15/PMD1/RB11 | bidirectional | Programming/debugging clock channel 2, JTAG test mode select, remappable RP11, PMP data bit 1 and PORTB bit 11. |
| 23 | AN12/DAC1RP/RP12/CN14/PMD0/RB12 | bidirectional | Analog input 12, DAC1 right channel positive output, remappable RP12, PMP data bit 0 and PORTB bit 12. |
| 24 | AN11/DAC1RN/RP13/CN13/PMRD/RB13 | bidirectional | Analog input 11, DAC1 right channel negative output, remappable RP13, PMP read strobe and PORTB bit 13. |
| 25 | AN10/DAC1LP/RTCC/RP14/CN12/PMWR/RB14 | bidirectional | Analog input 10, DAC1 left channel positive output, RTCC alarm output, remappable RP14, PMP write strobe and PORTB bit 14. |
| 26 | AN9/DAC1LN/RP15/CN11/PMCS1/RB15 | bidirectional | Analog input 9, DAC1 left channel negative output, remappable RP15, PMP chip select 1 and PORTB bit 15. |
| 27 | AVSS | power_in | Ground reference for analog modules. |
| 28 | AVDD | power_in | Positive supply for analog modules; must be connected at all times. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-28-300mil |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating supply voltage | VDD | 3 | 3.6 | V | -40ºC to +125ºC, DC to 40 MIPS | 1 | |
| Operating temperature | TA | -40 | 125 | ºC | DC to 40 MIPS | 1 | |
| CPU speed | 40 | MIPS | 3.0V to 3.6V, -40ºC to +125ºC | 1 | |||
| Overvoltage clamp current per pin | 5 | mA | Up to 5 mA overvoltage clamp current/pin | 1 | |||
| POR extension time | TPOR | 30 | μs | maximum | 83 | ||
| BOR extension time | TBOR | 100 | μs | maximum | 83 | ||
| Fail-Safe Clock Monitor Delay | TFSCM | 900 | μs | maximum | 83 | ||
| Oscillator start-up delay, FRC | TOSCD | 1.1 | μs | max for FRC | 81 | ||
| Oscillator start-up delay, LPRC | TOSCD | 70 | μs | max for LPRC | 81 | ||
| POR threshold | VPOR | 1.8 | V | nominal | 83 | ||
| BOR threshold | VBOR | 2.5 | V | nominal | 83 | ||
| PLL lock time | TLOCK | 1.5 | ms | nominal, if PLL is enabled | 81 | ||
| VCAP capacitor value | CEFC | 4.7 | 10 | µF | low-ESR (< 5 Ohms) capacitor on VCAP | 20 | |
| VCAP pin voltage | VCAP | 2.5 | V | VDD ≥ VDDMIN | 319 | ||
| Voltage regulator start-up time | TSTARTUP | 20 | μs | approximately, on POR | 319 |
CAD (KiCad official)
- Symbol:
dsPIC33FJ128GP802-E - Footprint:
Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm - 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
- 3D model files:
dspic33fj128gp802-e-etched.step/dspic33fj128gp802-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dspic33fj128gp802-e.step/dspic33fj128gp802-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (436 pp, sha256
7e540c84de50041b, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).