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dsPIC33FJ128GP206-I
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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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README
markdowndsPIC33FJ128GP206-I
Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-64(10x10)
dsPIC33FJ128GP206-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COFS/RG15 | bidirectional | DCI frame synchronization I/O or PORTG digital I/O RG15; 5V tolerant. |
| 2 | AN16/T2CK/T7CK/RC1 | bidirectional | Analog input AN16, Timer2/Timer7 external clock inputs or PORTC I/O RC1. |
| 3 | AN17/T3CK/T6CK/RC2 | bidirectional | Analog input AN17, Timer3/Timer6 external clock inputs or PORTC I/O RC2. |
| 4 | SCK2/CN8/RG6 | bidirectional | SPI2 serial clock I/O, change notification CN8 or PORTG I/O RG6; 5V tolerant. |
| 5 | SDI2/CN9/RG7 | bidirectional | SPI2 data in, change notification CN9 or PORTG I/O RG7; 5V tolerant. |
| 6 | SDO2/CN10/RG8 | bidirectional | SPI2 data out, change notification CN10 or PORTG I/O RG8; 5V tolerant. |
| 7 | MCLR | input | Active-low master clear (Reset) input, also used for device programming and debugging. |
| 8 | SS2/CN11/RG9 | bidirectional | SPI2 slave select/frame pulse I/O, change notification CN11 or PORTG I/O RG9; 5V tolerant. |
| 9 | VSS | power_in | Ground reference for logic and I/O pins. |
| 10 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V). |
| 11 | AN5/IC8/CN7/RB5 | bidirectional | Analog input AN5, input capture 8, change notification CN7 or PORTB I/O RB5. |
| 12 | AN4/IC7/CN6/RB4 | bidirectional | Analog input AN4, input capture 7, change notification CN6 or PORTB I/O RB4. |
| 13 | AN3/CN5/RB3 | bidirectional | Analog input AN3, change notification CN5 or PORTB I/O RB3. |
| 14 | AN2/SS1/CN4/RB2 | bidirectional | Analog input AN2, SPI1 slave select, change notification CN4 or PORTB I/O RB2. |
| 15 | PGEC3/AN1/VREF-/CN3/RB1 | bidirectional | Programming/debug clock channel 3, analog input AN1, ADC VREF- low reference, CN3 or PORTB I/O RB1. |
| 16 | PGED3/AN0/VREF+/CN2/RB0 | bidirectional | Programming/debug data channel 3, analog input AN0, ADC VREF+ high reference, CN2 or PORTB I/O RB0. |
| 17 | PGEC1/AN6/OCFA/RB6 | bidirectional | Programming/debug clock channel 1, analog input AN6, Compare Fault A input or PORTB I/O RB6. |
| 18 | PGED1/AN7/RB7 | bidirectional | Programming/debug data channel 1, analog input AN7 or PORTB I/O RB7. |
| 19 | AVDD | power_in | Positive supply for analog modules; must be connected at all times. |
| 20 | AVSS | power_in | Ground reference for analog modules. |
| 21 | U2CTS/AN8/RB8 | bidirectional | UART2 clear to send input, analog input AN8 or PORTB I/O RB8. |
| 22 | AN9/RB9 | bidirectional | Analog input AN9 or PORTB I/O RB9. |
| 23 | TMS/AN10/RB10 | bidirectional | JTAG test mode select input, analog input AN10 or PORTB I/O RB10. |
| 24 | TDO/AN11/RB11 | bidirectional | JTAG test data output, analog input AN11 or PORTB I/O RB11. |
| 25 | VSS | power_in | Ground reference for logic and I/O pins. |
| 26 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V). |
| 27 | TCK/AN12/RB12 | bidirectional | JTAG test clock input, analog input AN12 or PORTB I/O RB12. |
| 28 | TDI/AN13/RB13 | bidirectional | JTAG test data input, analog input AN13 or PORTB I/O RB13. |
| 29 | U2RTS/AN14/RB14 | bidirectional | UART2 ready to send output, analog input AN14 or PORTB I/O RB14. |
| 30 | AN15/OCFB/CN12/RB15 | bidirectional | Analog input AN15, Compare Fault B input, change notification CN12 or PORTB I/O RB15. |
| 31 | U2RX/CN17/RF4 | bidirectional | UART2 receive input, change notification CN17 or PORTF I/O RF4; 5V tolerant. |
| 32 | U2TX/CN18/RF5 | bidirectional | UART2 transmit output, change notification CN18 or PORTF I/O RF5; 5V tolerant. |
| 33 | U1TX/SDO1/RF3 | bidirectional | UART1 transmit output, SPI1 data out or PORTF I/O RF3; 5V tolerant. |
| 34 | U1RX/SDI1/RF2 | bidirectional | UART1 receive input, SPI1 data in or PORTF I/O RF2; 5V tolerant. |
| 35 | U1RTS/SCK1/INT0/RF6 | bidirectional | UART1 ready to send output, SPI1 clock I/O, external interrupt 0 or PORTF I/O RF6; 5V tolerant. |
| 36 | SDA1/RG3 | bidirectional | I2C1 serial data I/O or PORTG I/O RG3; 5V tolerant. |
| 37 | SCL1/RG2 | bidirectional | I2C1 serial clock I/O or PORTG I/O RG2; 5V tolerant. |
| 38 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V). |
| 39 | OSC1/CLKIN/RC12 | bidirectional | Oscillator crystal input or external clock input (CLKI), or PORTC I/O RC12. |
| 40 | OSC2/CLKO/RC15 | bidirectional | Oscillator crystal output or CLKO in RC and EC modes, or PORTC I/O RC15. |
| 41 | VSS | power_in | Ground reference for logic and I/O pins. |
| 42 | IC1/INT1/RD8 | bidirectional | Input capture 1, external interrupt 1 or PORTD I/O RD8; 5V tolerant. |
| 43 | IC2/U1CTS/INT2/RD9 | bidirectional | Input capture 2, UART1 clear to send, external interrupt 2 or PORTD I/O RD9; 5V tolerant. |
| 44 | IC3/INT3/RD10 | bidirectional | Input capture 3, external interrupt 3 or PORTD I/O RD10; 5V tolerant. |
| 45 | IC4/INT4/RD11 | bidirectional | Input capture 4, external interrupt 4 or PORTD I/O RD11; 5V tolerant. |
| 46 | OC1/RD0 | bidirectional | Output compare 1 or PORTD I/O RD0; 5V tolerant. |
| 47 | PGED2/SOSCI/T4CK/CN1/RC13 | bidirectional | Programming/debug data channel 2, 32.768 kHz secondary oscillator input, Timer4 clock, CN1 or PORTC I/O RC13. |
| 48 | PGEC2/SOSCO/T1CK/CN0/RC14 | bidirectional | Programming/debug clock channel 2, 32.768 kHz secondary oscillator output, Timer1 clock, CN0 or PORTC I/O RC14. |
| 49 | OC2/RD1 | bidirectional | Output compare 2 or PORTD I/O RD1; 5V tolerant. |
| 50 | OC3/RD2 | bidirectional | Output compare 3 or PORTD I/O RD2; 5V tolerant. |
| 51 | OC4/RD3 | bidirectional | Output compare 4 or PORTD I/O RD3; 5V tolerant. |
| 52 | OC5/IC5/CN13/RD4 | bidirectional | Output compare 5, input capture 5, change notification CN13 or PORTD I/O RD4; 5V tolerant. |
| 53 | OC6/IC6/CN14/RD5 | bidirectional | Output compare 6, input capture 6, change notification CN14 or PORTD I/O RD5; 5V tolerant. |
| 54 | OC7/CN15/RD6 | bidirectional | Output compare 7, change notification CN15 or PORTD I/O RD6; 5V tolerant. |
| 55 | OC8/CN16/RD7 | bidirectional | Output compare 8, change notification CN16 or PORTD I/O RD7; 5V tolerant. |
| 56 | VCAP/VDDCORE | passive | CPU core regulator filter capacitor connection; requires a 4.7 µF to 10 µF low-ESR (<5 ohm) capacitor to ground and must not be connected to VDD. |
| 57 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V). |
| 58 | RF0 | bidirectional | PORTF digital I/O RF0; 5V tolerant. |
| 59 | RF1 | bidirectional | PORTF digital I/O RF1; 5V tolerant. |
| 60 | RG1 | bidirectional | PORTG digital I/O RG1; 5V tolerant. |
| 61 | RG0 | bidirectional | PORTG digital I/O RG0; 5V tolerant. |
| 62 | CSCK/RG14 | bidirectional | DCI serial clock I/O or PORTG I/O RG14; 5V tolerant. |
| 63 | CSDI/RG12 | bidirectional | DCI serial data input or PORTG I/O RG12; 5V tolerant. |
| 64 | CSDO/RG13 | bidirectional | DCI serial data output or PORTG I/O RG13; 5V tolerant. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-64(10x10) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 3 | 3.6 | V | 261 | ||
| RAM Data Retention Voltage | VDR | 1.8 | V | 261 | |||
| VDD Rise Rate to ensure internal POR | SVDD | 0.03 | V/ms | 0-3.0V in 0.1s | 261 | ||
| VDD Core internal regulator voltage | VCORE | 2.25 | 2.75 | V | Voltage is dependent on load, temperature and VDD | 261 | |
| Operating Ambient Temperature Range | TA | -40 | 85 | °C | 260 | ||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | 260 | ||
| Package Thermal Resistance, 64-pin TQFP (10x10x1 mm) | θJA | 40 | °C/W | 260 | |||
| Max MIPS | 40 | MIPS | 3.0-3.6V, -40°C to +85°C | 260 | |||
| Operating Current | IDD | 84 | 90 | mA | +25°C, 3.3V, 40 MIPS | 262 | |
| Operating Current | IDD | 27 | 30 | mA | +25°C, 3.3V, 10 MIPS | 262 | |
| Idle Current | IIDLE | 16 | 25 | mA | +25°C, 3.3V, 40 MIPS | 263 | |
| Base Power-Down Current | IPD | 211 | 500 | μA | +25°C, 3.3V | 264 | |
| Base Power-Down Current | IPD | 244 | 500 | μA | +85°C, 3.3V | 264 | |
| Watchdog Timer Current | ΔIWDT | 12 | 20 | μA | +85°C, 3.3V | 264 | |
| Input Low Voltage, I/O pins | VIL | 0 | 0.2 | V | max is 0.2 VDD; min VSS | 265 | |
| Input High Voltage, I/O pins 5V tolerant | VIH | 2 | 5.5 | V | VDD = 3.3V | 265 | |
| CNx Pull-up Current | ICNPU | 50 | 250 | 400 | μA | VDD = 3.3V, VPIN = VSS | 265 |
| Input Leakage Current, I/O pins | IIL | -2 | 2 | μA | VSS ≤ VPIN ≤ VDD, Pin at high-impedance | 265 | |
| Output Low Voltage, I/O ports | VOL | 0.4 | V | IOL = 2 mA, VDD = 3.3V | 266 | ||
| Output High Voltage, I/O ports | VOH | 2.4 | V | IOH = -2.3 mA, VDD = 3.3V | 266 | ||
| BOR Event on VDD transition high-to-low | VBOR | 2.4 | 2.55 | V | 266 | ||
| External Filter Capacitor Value | CEFC | 4.7 | 10 | μF | Capacitor must be low series resistance (< 5 ohms) | 267 | |
| Internal FRC Accuracy | FRC | -2 | 2 | % | -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V | 270 | |
| Internal LPRC Accuracy | LPRC | -20 | 6 | 20 | % | -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V | 270 |
| PLL VCO Input Frequency | FPLLI | 0.8 | 8 | MHz | ECPLL, HSPLL, XTPLL modes | 270 | |
| On-Chip VCO System Frequency | FSYS | 100 | 200 | MHz | 270 | ||
| PLL Lock Time | TLOCK | 0.9 | 1.5 | 3.1 | ms | 270 | |
| External CLKI Frequency | FIN | 40 | MHz | EC | 269 | ||
| Instruction Cycle Time | TCY | 25 | ns | 269 | |||
| Program Flash Cell Endurance | EP | 100 | 1000 | E/W | See Note 2 | 267 | |
| Characteristic Retention | TRETD | 20 | Year | Provided no other specifications are violated | 267 | ||
| Power-on Reset Delay | TPOR | 3 | 10 | 30 | μs | -40°C to +85°C | 273 |
| Ambient temperature under bias | -40 | 85 | °C | 259 | |||
| Storage temperature | -65 | 150 | °C | 259 | |||
| Voltage on VDD with respect to VSS | VDD | -0.3 | 4 | V | 259 | ||
| Voltage on any combined analog and digital pin and MCLR | -0.3 | V | max is VDD + 0.3V, with respect to VSS | 259 | |||
| Voltage on any digital-only pin | -0.3 | 5.6 | V | with respect to VSS | 259 | ||
| Voltage on VCAP/VDDCORE | 2.25 | 2.75 | V | with respect to VSS | 259 | ||
| Maximum output current sunk by any I/O pin | 4 | mA | 259 | ||||
| Maximum output current sourced by any I/O pin | 4 | mA | 259 |
CAD (KiCad official)
- Symbol:
dsPIC33FJ128GP206-I - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
dspic33fj128gp206-i-etched.step/dspic33fj128gp206-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dspic33fj128gp206-i.step/dspic33fj128gp206-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (322 pp, sha256
f1b54d2d097540e1, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).