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dsPIC33EP32GS506-I

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Microchip Tech Digital Signal Processors / Controllers (DSPs/DSCs), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollerdspic33ep32gs506-ifactory-2.0.0extractor-text

Changed since verified dsPIC33EP32GS506-I

by Ray · last 2 Nov 2026 · 1 record · files changed since
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 64 pinschanged since
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: dsPIC33EP32GS506-I · TQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 390-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: TQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-9bhx6y8u/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! dspic33ep32gs506-i.kicad_sym✓ dspic33ep32gs506-i.kicad_mod✓ dspic33ep32gs506-i.step
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dsPIC33EP32GS506-I

Microchip Tech · Digital Signal Processors / Controllers (DSPs/DSCs) · TQFP-64(10x10)

dsPIC33EP32GS506-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PWM4L/RD3 output PWM Low Output 4 (PWM4L), a PWM generator output on PORTD bit 3 that is available on 64-pin devices.
2 PWM1H/RA4 output PWM High Output 1 (PWM1H), a PWM generator output that shares PORTA bit 4.
3 PWM1L/RA3 output PWM Low Output 1 (PWM1L), a PWM generator output that shares PORTA bit 3.
4 FLT12/RP48/RC0 input PWM Fault Input 12 (FLT12), a Schmitt Trigger input that can also be remapped via Peripheral Pin Select (RP48) and shares PORTC bit 0.
5 FLT11/RP61/RC13 input PWM Fault Input 11 (FLT11), a Schmitt Trigger input that can also be remapped via Peripheral Pin Select (RP61) and shares PORTC bit 13.
6 FLT10/RD10 input PWM Fault Input 10 (FLT10), a Schmitt Trigger input that shares PORTD bit 10.
7 MCLR input Master Clear (Reset) input, an active-low Reset to the device.
8 FLT9/T5CK/RD12 input PWM Fault Input 9 (FLT9), which also serves as the Timer5 external clock input (T5CK) and shares PORTD bit 12.
9 VSS power_in Ground reference for logic and I/O pins; must be connected at all times.
10 VDD power_in Positive supply for peripheral logic and I/O pins; must be connected at all times.
11 AN12/ISRC1/RP59/RC11 passive Analog input channel AN12, which also serves as Constant-Current Source output ISRC1 and shares PORTC bit 11.
12 AN14/PGA2N3/RP60/RC12 passive Analog input channel AN14, which also serves as PGA2 negative input 3 (PGA2N3) and shares PORTC bit 12.
13 AN0/PGA1P1/CMP1A/RA0 passive Analog input channel AN0, which also serves as PGA1 positive input 1 (PGA1P1) and Comparator 1 input A (CMP1A), and shares PORTA bit 0.
14 AN1/PGA1P2/PGA2P1/CMP1B/RA1 passive Analog input channel AN1, which also serves as PGA1 positive input 2 and PGA2 positive input 1, and shares PORTA bit 1.
15 AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2 passive Analog input channel AN2, which also serves as PGA1 positive input 3, PGA2 positive input 2, and Comparator inputs CMP1C and CMP2A, and shares PORTA bit 2.
16 AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0 passive Analog input channel AN3, which also serves as PGA2 positive input 3 and Comparator inputs CMP1D and CMP2B, and shares PORTB bit 0.
17 AN4/CMP2C/CMP3A/ISRC4/RP41/RB9 passive Analog input channel AN4, which also serves as Comparator inputs CMP2C and CMP3A and Constant-Current Source output ISRC4, and shares PORTB bit 9.
18 AN5/CMP2D/CMP3B/ISRC3/RP42/RB10 passive Analog input channel AN5, which also serves as Comparator inputs CMP2D and CMP3B and Constant-Current Source output ISRC3, and shares PORTB bit 10.
19 AVDD power_in Positive supply for analog modules; must be connected at all times.
20 AVSS power_in Ground reference for analog modules; must be connected at all times.
21 AN15/RD7 passive Analog input channel AN15, which shares PORTD bit 7.
22 AN13/DACOUT2/RD13 passive Analog input channel AN13, which also serves as DAC Output Voltage 2 (DACOUT2) and shares PORTD bit 13.
23 AN11/PGA1N3/RP57/RC9 passive Analog input channel AN11, which also serves as PGA1 negative input 3 (PGA1N3) and shares PORTC bit 9.
24 AN10/PGA1P4/EXTREF2/RP58/RC10 passive Analog input channel AN10, which also serves as PGA1 positive input 4 and External Voltage Reference Input 2 (EXTREF2), and shares PORTC bit 10.
25 VSS power_in Ground reference for logic and I/O pins; must be connected at all times.
26 VDD power_in Positive supply for peripheral logic and I/O pins; must be connected at all times.
27 AN8/PGA2P4/CMP4C/RP49/RC1 passive Analog input channel AN8, which also serves as PGA2 positive input 4 and Comparator input CMP4C, and shares PORTC bit 1.
28 OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1 input Oscillator crystal input and external clock source input (CLKI), which also serves as analog input AN6 and shares PORTB bit 1.
29 OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2 output Oscillator crystal output and reference clock output (CLKO) connecting to the crystal in Crystal Oscillator mode, which also serves as analog input AN7 and shares PORTB bit 2.
30 AN16/RD2 passive Analog input channel AN16, which shares PORTD bit 2.
31 ASDA2/RP63/RC15 bidirectional Alternate synchronous serial data input/output for I2C2 (ASDA2), which can also be remapped via Peripheral Pin Select (RP63) and shares PORTC bit 15.
32 PGED2/AN18/DACOUT1/ASCL2/INT0/RP35/RB3 bidirectional Data I/O pin for programming/debugging Communication Channel 2 (PGED2), which also serves as analog input AN18, DAC Output 1, External Interrupt 0 and shares PORTB bit 3.
33 PGEC2/ADTRG31/RP36/RB4 input Clock input pin for programming/debugging Communication Channel 2 (PGEC2), which also serves as the external ADC trigger source ADTRG31 and shares PORTB bit 4.
34 RP62/RC14 bidirectional Remappable peripheral pin RP62 that shares PORTC bit 14 and supports Peripheral Pin Select functions.
35 AN9/CMP4D/EXTREF1/RP50/RC2 passive Analog input channel AN9, which also serves as Comparator input CMP4D and External Voltage Reference Input 1 (EXTREF1), and shares PORTC bit 2.
36 ASDA1/RP55/RC7 bidirectional Alternate synchronous serial data input/output for I2C1 (ASDA1), which can also be remapped via Peripheral Pin Select (RP55) and shares PORTC bit 7.
37 ASCL1/RP56/RC8 bidirectional Alternate synchronous serial clock input/output for I2C1 (ASCL1), which can also be remapped via Peripheral Pin Select (RP56) and shares PORTC bit 8.
38 VDD power_in Positive supply for peripheral logic and I/O pins; must be connected at all times.
39 RD14 bidirectional General purpose bidirectional I/O on PORTD bit 14.
40 RD9 bidirectional General purpose bidirectional I/O on PORTD bit 9.
41 VSS power_in Ground reference for logic and I/O pins; must be connected at all times.
42 RD8 bidirectional General purpose bidirectional I/O on PORTD bit 8.
43 PGED3/SDA2/FLT31/RP40/RB8 bidirectional Data I/O pin for programming/debugging Communication Channel 3 (PGED3), which also serves as I2C2 data (SDA2) and PWM Class B Fault Input 31 (FLT31), and shares PORTB bit 8.
44 PGEC3/SCL2/RP47/RB15 input Clock input pin for programming/debugging Communication Channel 3 (PGEC3), which also serves as I2C2 clock (SCL2) and shares PORTB bit 15.
45 INT4/RD11 input External Interrupt 4 (INT4), which is not remappable and shares PORTD bit 11.
46 TDO/AN19/PGA2N2/RP37/RB5 output JTAG test data output pin (TDO), which also serves as analog input AN19 and PGA2 negative input 2, and shares PORTB bit 5.
47 T4CK/RD0 input Timer4 external clock input (T4CK), which shares PORTD bit 0.
48 PGED1/TDI/AN20/SCL1/RP38/RB6 bidirectional Data I/O pin for programming/debugging Communication Channel 1 (PGED1), which also serves as JTAG test data input (TDI) and I2C1 clock (SCL1), and shares PORTB bit 6.
49 PGEC1/AN21/SDA1/RP39/RB7 input Clock input pin for programming/debugging Communication Channel 1 (PGEC1), which also serves as analog input AN21 and I2C1 data (SDA1), and shares PORTB bit 7.
50 AN1ALT/RP52/RC4 passive Alternate analog input channel AN1ALT, which can also be remapped via Peripheral Pin Select (RP52) and shares PORTC bit 4.
51 AN0ALT/RP53/RC5 passive Alternate analog input channel AN0ALT, which can also be remapped via Peripheral Pin Select (RP53) and shares PORTC bit 5.
52 AN17/RP54/RC6 passive Analog input channel AN17, which can also be remapped via Peripheral Pin Select (RP54) and shares PORTC bit 6.
53 RD5 bidirectional General purpose bidirectional I/O on PORTD bit 5.
54 PWM5H/RD6 output PWM High Output 5 (PWM5H), a PWM generator output that shares PORTD bit 6.
55 PWM5L/RP51/RC3 output PWM Low Output 5 (PWM5L), a PWM generator output that can also be remapped via Peripheral Pin Select (RP51) and shares PORTC bit 3.
56 VCAP passive CPU logic filter capacitor connection; a low-ESR capacitor greater than 4.7 µF is required and VCAP must not be connected to VDD.
57 VDD power_in Positive supply for peripheral logic and I/O pins; must be connected at all times.
58 RD4 bidirectional General purpose bidirectional I/O on PORTD bit 4.
59 RD15 bidirectional General purpose bidirectional I/O on PORTD bit 15.
60 TMS/PWM3H/RP43/RB11 input JTAG test mode select pin (TMS), which also serves as PWM High Output 3 (PWM3H) and shares PORTB bit 11.
61 TCK/PWM3L/RP44/RB12 input JTAG test clock input pin (TCK), which also serves as PWM Low Output 3 (PWM3L) and shares PORTB bit 12.
62 PWM2H/RP45/RB13 output PWM High Output 2 (PWM2H), a PWM generator output that can also be remapped via Peripheral Pin Select (RP45) and shares PORTB bit 13.
63 PWM2L/RP46/RB14 output PWM Low Output 2 (PWM2L), a PWM generator output that can also be remapped via Peripheral Pin Select (RP46) and shares PORTB bit 14.
64 PWM4H/RD1 output PWM High Output 4 (PWM4H), a PWM generator output that shares PORTD bit 1 and is available on 64-pin devices.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-64(10x10)
Category Single Chip Microcomputer/Microcontroller
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD 3 3.6 V Standard Operating Conditions: 3.0V to 3.6V 305
Voltage on VDD with respect to VSS VDD -0.3 4 V With respect to VSS 303
Voltage on any 5V tolerant pin with respect to VSS when VDD >= 3.0V -0.3 5.5 V When VDD >= 3.0V 303
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V -0.3 3.6 V When VDD < 3.0V 303
Voltage on any pin that is not 5V tolerant with respect to VSS -0.3 V Upper limit printed as (VDD + 0.3V) 303
Ambient temperature under bias -40 125 °C 303
Storage temperature -65 150 °C 303
Operating Junction Temperature Range (Industrial) TJ -40 125 °C Industrial Temperature Devices 304
Operating Ambient Temperature Range (Industrial) TA -40 85 °C Industrial Temperature Devices 304
Maximum MIPS 70 MIPS VDD 3.0V to 3.6V, -40°C to +85°C 304
Package Thermal Resistance, 64-Pin TQFP 10x10x1 mm JA 49 °C/W Note 1: junction to ambient thermal resistance 304
VDD Supply Voltage (DC10) VDD 3 3.6 V Standard Operating Conditions: 3.0V to 3.6V 305
RAM Retention Voltage (DC12) VDR 1.8 V -40ºC 305
RAM Retention Voltage (DC12) VDR 2 V +25ºC, +85ºC, +125ºC 305
VDD Rise Rate to Ensure Internal Power-on Reset Signal (DC17) SVDD 1 V/ms 0V-3V in 3 ms 305
External Filter Capacitor Value (CEFC) CEFC 4.7 10 F Capacitor must have a low series resistance (<1 ohm) 305

CAD (KiCad official)

  • Symbol: dsPIC33EP32GS506-I
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: dspic33ep32gs506-i-etched.step / dspic33ep32gs506-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dspic33ep32gs506-i.step / dspic33ep32gs506-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (390 pp, sha256 69126c50f4a4115e, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF