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dsPIC33CK64MP105-I/PT

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Microchip Tech MICROCHIP, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersdspic33ck64mp105-ifactory-2.0.0extractor-text

Verified dsPIC33CK64MP105-I/PT

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier mfr, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: dsPIC33CK64MP105-I/PT · TQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 530-page datasheet
  • ✓distributor: lcsc C648131, digikey DSPIC33CK64MP105-I/PT-ND, mouser 579-DSPIC33CK6405PT
  • ✓family: TQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-tw2yu2ix/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.509)
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 59 kB, viewers/symbol.html 34 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dspic33ck64mp105-i-pt.kicad_sym✓ dspic33ck64mp105-i-pt.kicad_mod✓ dspic33ck64mp105-i-pt.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray
viewers dspic33ck64mp105-i-pt: viewers rendered from the public page · Ray
dspic33ck64mp105-i-pt-etched.glb dspic33ck64mp105-i-pt: factory component page (tier=mfr) · Ray
dspic33ck64mp105-i-pt-etched.step dspic33ck64mp105-i-pt: factory component page (tier=mfr) · Ray
dspic33ck64mp105-i-pt-hero.glb dspic33ck64mp105-i-pt: hero GLB from the etched model (keeps the MPN mark) · Ray
dspic33ck64mp105-i-pt-hero.overlay.json dspic33ck64mp105-i-pt: hero GLB from the etched model (keeps the MPN mark) · Ray
dspic33ck64mp105-i-pt.glb Publish 0.1.0 · Ray
dspic33ck64mp105-i-pt.kicad_mod Publish 0.1.0 · Ray
dspic33ck64mp105-i-pt.kicad_sym Publish 0.1.0 · Ray
dspic33ck64mp105-i-pt.lbr Publish 0.1.0 · Ray
dspic33ck64mp105-i-pt.step Publish 0.1.0 · Ray
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page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 48 pins · Ray

dsPIC33CK64MP105-I

Microchip Tech · MICROCHIP · TQFP-48(7x7)

dsPIC33CK64MP105-I from Microchip Tech, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RP46/PWM1H/RB14 bidirectional Remappable pin RP46 (PPS) that can carry the PWM1H high output or serve as PORTB bit RB14, a Schmitt-trigger bidirectional I/O.
2 RP47/PWM1L/RB15 bidirectional Remappable pin RP47 (PPS) that can carry the PWM1L low output or serve as PORTB bit RB15, a Schmitt-trigger bidirectional I/O.
3 RP60/RC12 bidirectional Remappable pin RP60 (PPS) or PORTC bit RC12, a Schmitt-trigger bidirectional I/O.
4 RP61/RC13 bidirectional Remappable pin RP61 (PPS) or PORTC bit RC13, a Schmitt-trigger bidirectional I/O.
5 MCLR input Master Clear input; an active-low Reset to the device.
6 ANN2/RP77/RD13 input Analog negative input ANN2, also remappable pin RP77 (PPS) or PORTD bit RD13.
7 AN12/ANN0/RP48/RC0 input Analog input AN12 and analog negative input ANN0, also remappable pin RP48 (PPS) or PORTC bit RC0.
8 OA1OUT/AN0/CMP1A/IBIAS0/RA0 output Op Amp 1 output, also analog input AN0, comparator 1A input, IBIAS0 current output and PORTA bit RA0.
9 OA1IN-/ANA1/RA1 input Op Amp 1 inverting input, also alternate analog input ANA1 and PORTA bit RA1.
10 OA1IN+/AN9/RA2 input Op Amp 1 non-inverting input, also analog input AN9 and PORTA bit RA2.
11 DACOUT/AN3/CMP1C/RA3 output DAC output voltage (DACOUT), also analog input AN3, comparator 1C input and PORTA bit RA3.
12 OA3OUT/AN4/CMP3B/IBIAS3/RA4 output Op Amp 3 output, also analog input AN4, comparator 3B input, IBIAS3 current output and PORTA bit RA4.
13 AVDD power_in Positive supply for analog modules; this pin must be connected at all times.
14 AVSS power_in Ground reference for analog modules; this pin must be connected at all times.
15 OA3IN-/AN13/CMP1B/ISRC0/RP49/RC1 input Op Amp 3 inverting input, also analog input AN13, comparator 1B input, ISRC0 10 µA constant-current output, remappable RP49 and PORTC bit RC1.
16 OA3IN+/AN14/CMP2B/ISRC1/RP50/RC2 input Op Amp 3 non-inverting input, also analog input AN14, comparator 2B input, ISRC1 10 µA constant-current output, remappable RP50 and PORTC bit RC2.
17 AN17/ANN1/IBIAS1/RP54/RC6 input Analog input AN17 and analog negative input ANN1, also IBIAS1 50 µA current output, remappable RP54 and PORTC bit RC6.
18 VDD power_in Positive supply for peripheral logic and I/O pins.
19 VSS power_in Ground reference for logic and I/O pins.
20 AN15/CMP2A/IBIAS2/RP51/RC3 input Analog input AN15, also comparator 2A input, IBIAS2 current output, remappable RP51 and PORTC bit RC3.
21 OSCI/CLKI/AN5/RP32/RB0 input Oscillator crystal input (OSCI) or external clock input (CLKI), also analog input AN5, remappable RP32 and PORTB bit RB0.
22 OSCO/CLKO/AN6/RP33/RB1(2,4) bidirectional Oscillator crystal output (OSCO) or CPU clock output (CLKO), also analog input AN6, remappable RP33 and PORTB bit RB1; this pin has increased current drive and is toggled during programming.
23 AN18/CMP3C/ISRC3/RP74/RD10 input Analog input AN18, also comparator 3C input, ISRC3 10 µA constant-current output, remappable RP74 and PORTD bit RD10.
24 AN16/ISRC2/RP55/RC7 input Analog input AN16, also ISRC2 10 µA constant-current output, remappable RP55 and PORTC bit RC7.
25 OA2OUT/AN1/AN7/ANA0/CMP1D/CMP2D/CMP3D/RP34/INT0/RB2 output Op Amp 2 output, also analog inputs AN1/AN7/ANA0, comparator 1D/2D/3D inputs, remappable RP34, external interrupt INT0 and PORTB bit RB2.
26 PGD2/OA2IN-/AN8/RP35/RB3 bidirectional Programming/debugging data pin PGD2 for channel 2, also Op Amp 2 inverting input, analog input AN8, remappable RP35 and PORTB bit RB3.
27 PGC2/OA2IN+/RP36/RB4 input Programming/debugging clock pin PGC2 for channel 2, also Op Amp 2 non-inverting input, remappable RP36 and PORTB bit RB4.
28 RP56/ASDA1/SCK2/RC8(2) bidirectional Remappable pin RP56 (PPS) that can carry alternate I2C1 data ASDA1, SPI2 clock SCK2 or PORTC bit RC8; this pin has increased current drive.
29 RP57/ASCL1/SDI2/RC9(2) bidirectional Remappable pin RP57 (PPS) that can carry alternate I2C1 clock ASCL1, SPI2 data input SDI2 or PORTC bit RC9; this pin has increased current drive.
30 RP72/SDO2/PCI19/RD8(2) bidirectional Remappable pin RP72 (PPS) that can carry SPI2 data output SDO2, PWM input PCI19 or PORTD bit RD8; this pin has increased current drive.
31 VSS power_in Ground reference for logic and I/O pins.
32 VDD power_in Positive supply for peripheral logic and I/O pins.
33 PGD3/RP37/SDA2/RB5 bidirectional Programming/debugging data pin PGD3 for channel 3, also remappable pin RP37, I2C2 data SDA2 and PORTB bit RB5.
34 PGC3/RP38/SCL2/RB6 input Programming/debugging clock pin PGC3 for channel 3, also remappable pin RP38, I2C2 clock SCL2 and PORTB bit RB6.
35 TDO/AN2/CMP3A/RP39/RB7 output JTAG test data output (TDO), also analog input AN2, comparator 3A input, remappable RP39 and PORTB bit RB7.
36 PGD1/AN10/RP40/SCL1/RB8 bidirectional Programming/debugging data pin PGD1 for channel 1, also analog input AN10, remappable RP40, I2C1 clock SCL1 and PORTB bit RB8.
37 PGC1/AN11/RP41/SDA1/RB9 input Programming/debugging clock pin PGC1 for channel 1, also analog input AN11, remappable RP41, I2C1 data SDA1 and PORTB bit RB9.
38 RP52/ASDA2/RC4 bidirectional Remappable pin RP52 (PPS) that can carry alternate I2C2 data ASDA2 or PORTC bit RC4, a Schmitt-trigger bidirectional I/O.
39 RP53/ASCL2/RC5 bidirectional Remappable pin RP53 (PPS) that can carry alternate I2C2 clock ASCL2 or PORTC bit RC5, a Schmitt-trigger bidirectional I/O.
40 RP58/RC10 bidirectional Remappable pin RP58 (PPS) or PORTC bit RC10, a Schmitt-trigger bidirectional I/O.
41 RP59/RC11 bidirectional Remappable pin RP59 (PPS) or PORTC bit RC11, a Schmitt-trigger bidirectional I/O.
42 VSS power_in Ground reference for logic and I/O pins.
43 VDD power_in Positive supply for peripheral logic and I/O pins.
44 RP65/PWM4H/RD1 bidirectional Remappable pin RP65 (PPS) that can carry the PWM4H high output or serve as PORTD bit RD1.
45 TMS/RP42/PWM3H/RB10(3) input JTAG test mode select input (TMS), also remappable pin RP42, PWM3H high output and PORTB bit RB10; a pull-up is connected during programming or when JTAG is enabled.
46 TCK/RP43/PWM3L/RB11 input JTAG test clock input (TCK), also remappable pin RP43, PWM3L low output and PORTB bit RB11.
47 TDI/RP44/PWM2H/RB12 input JTAG test data input (TDI), also remappable pin RP44, PWM2H high output and PORTB bit RB12.
48 RP45/PWM2L/RB13 bidirectional Remappable pin RP45 (PPS) that can carry the PWM2L low output or serve as PORTB bit RB13.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -40 125 °C 465
Storage temperature -65 150 °C 465
Voltage on VDD with respect to VSS VDD -0.3 4 V 465
Voltage on any pin that is not 5V tolerant with respect to VSS -0.3 V Max printed as VDD + 0.3V 465
Voltage on any 5V tolerant pin with respect to VSS -0.3 5.5 V 465
Supply voltage VDD 3 3.6 V 466
Maximum CPU clock frequency 100 MHz VDD 3.0V to 3.6V, -40°C to +125°C 466
Operating ambient temperature range TA -40 85 °C Industrial temperature devices 466
Operating junction temperature range TJ -40 125 °C Industrial temperature devices 466
VDD rise rate to ensure internal power-on reset signal (DC17) SVDD 0.03 V/ms 0V-3V in 100 ms 466
BOR event on VDD transition high-to-low (BO10) VBOR 2.65 2.95 V BOR event on VDD transition high-to-low 466
Operating current IDD (DC20), 10 MIPS IDD 5.5 6.7 mA -40°C, 3.3V, 10 MIPS (N = 1, N2 = 5, N3 = 2, M = 50, FVCO = 400 MHz, FPLLO = 40 MHz) 467
Operating current IDD (DC20), 10 MIPS IDD 5.6 6.9 mA +25°C, 3.3V, 10 MIPS (N = 1, N2 = 5, N3 = 2, M = 50, FVCO = 400 MHz, FPLLO = 40 MHz) 467
Operating current IDD (DC20), 10 MIPS IDD 6.3 9.5 mA +85°C, 3.3V, 10 MIPS (N = 1, N2 = 5, N3 = 2, M = 50, FVCO = 400 MHz, FPLLO = 40 MHz) 467
Operating current IDD (DC21), 20 MIPS IDD 7.5 11 mA -40°C, 3.3V, 20 MIPS (N = 1, N2 = 5, N3 = 1, M = 60, FVCO = 480 MHz, FPLLO = 280 MHz) 467
Operating current IDD (DC21), 20 MIPS IDD 7.6 9.1 mA +25°C, 3.3V, 20 MIPS (N = 1, N2 = 5, N3 = 1, M = 60, FVCO = 480 MHz, FPLLO = 280 MHz) 467
Operating current IDD (DC21), 20 MIPS IDD 8.3 11.7 mA +85°C, 3.3V, 20 MIPS (N = 1, N2 = 5, N3 = 1, M = 60, FVCO = 480 MHz, FPLLO = 280 MHz) 467
Operating current IDD (DC22), 40 MIPS IDD 10.7 15.8 mA -40°C, 3.3V, 40 MIPS (N = 1, N2 = 3, N3 = 1, M = 60, FVCO = 480 MHz, FPLLO = 160 MHz) 467
Operating current IDD (DC22), 40 MIPS IDD 10.8 12.7 mA +25°C, 3.3V, 40 MIPS (N = 1, N2 = 3, N3 = 1, M = 60, FVCO = 480 MHz, FPLLO = 160 MHz) 467
Operating current IDD (DC22), 40 MIPS IDD 11.6 15.3 mA +85°C, 3.3V, 40 MIPS (N = 1, N2 = 3, N3 = 1, M = 60, FVCO = 480 MHz, FPLLO = 160 MHz) 467
Operating current IDD (DC23), 70 MIPS IDD 16.6 25.8 mA -40°C, 3.3V, 70 MIPS (N = 1, N2 = 2, N3 = 1, M = 70, FVCO = 560 MHz, FPLLO = 280 MHz) 467
Operating current IDD (DC23), 70 MIPS IDD 16.9 19.4 mA +25°C, 3.3V, 70 MIPS (N = 1, N2 = 2, N3 = 1, M = 70, FVCO = 560 MHz, FPLLO = 280 MHz) 467
Operating current IDD (DC23), 70 MIPS IDD 17.7 22 mA +85°C, 3.3V, 70 MIPS (N = 1, N2 = 2, N3 = 1, M = 70, FVCO = 560 MHz, FPLLO = 280 MHz) 467
Operating current IDD (DC24), 90 MIPS IDD 21.1 32.7 mA -40°C, 3.3V, 90 MIPS (N = 1, N2 = 2, N3 = 1, M = 90, FVCO = 720 MHz, FPLLO = 360 MHz) 467
Operating current IDD (DC24), 90 MIPS IDD 21.4 24.5 mA +25°C, 3.3V, 90 MIPS (N = 1, N2 = 2, N3 = 1, M = 90, FVCO = 720 MHz, FPLLO = 360 MHz) 467
Operating current IDD (DC24), 90 MIPS IDD 22.1 27 mA +85°C, 3.3V, 90 MIPS (N = 1, N2 = 2, N3 = 1, M = 90, FVCO = 720 MHz, FPLLO = 360 MHz) 467
Operating current IDD (DC25), 100 MIPS IDD 20.7 33.9 mA -40°C, 3.3V, 100 MIPS (N = 1, N2 = 1, N3 = 1, M = 50, FVCO = 400 MHz, FPLLO = 400 MHz) 467
Operating current IDD (DC25), 100 MIPS IDD 21 24.1 mA +25°C, 3.3V, 100 MIPS (N = 1, N2 = 1, N3 = 1, M = 50, FVCO = 400 MHz, FPLLO = 400 MHz) 467
Operating current IDD (DC25), 100 MIPS IDD 21.4 26.2 mA +85°C, 3.3V, 100 MIPS (N = 1, N2 = 1, N3 = 1, M = 50, FVCO = 400 MHz, FPLLO = 400 MHz) 467
Comparator + DAC delta current (DC130) 1.2 1.35 mA -40°C, 3.3V, AFPLLO @ 500 MHz 472
Comparator + DAC delta current (DC130) 1.23 1.65 mA +25°C, 3.3V, AFPLLO @ 500 MHz 472
Op amp delta current (DC140) 0.25 1 mA -40°C, 3.3V 472
Op amp delta current (DC140) 0.27 1.1 mA +25°C, 3.3V 472
Op amp delta current (DC140) 0.32 1.4 mA +85°C, 3.3V 472
Input high-level voltage, 5V tolerant I/O pins and MCLR (DI20) VIH 5.5 V Min printed as 0.8 VDD 473
Input current with pull-up resistor enabled (DI30) ICNPU 175 545 µA VDD = 3.3V, VPIN = VSS 473
Input current with pull-down resistor enabled (DI31) ICNPD 65 360 µA VDD = 3.3V, VPIN = VDD 473
Input leakage current, I/O pins and MCLR (DI50) IIL -1 µA VPIN = VSS 473
Input leakage current, I/O pins and MCLR (DI50) IIL 1 µA VPIN = VDD 473
Input low injection current (DI60a) IICL 0 -5 mA This parameter applies to all pins 474
Input high injection current (DI60b) IICH 0 5 mA Applies to all pins except all 5V tolerant pins and SOSCI 474
Total input injection current, sum of all I/O and control pins (DI60c) IICT -20 20 mA Absolute instantaneous sum of all ± input injection currents from all I/O pins 474
Cell endurance (D130) EP 10000 E/W 475
Characteristic retention (D134) TRETD 20 Year 475
Port output rise time (DO31) TIOR 10 ns Characterized but not tested in manufacturing 477
Port output fall time (DO32) TIOF 10 ns Characterized but not tested in manufacturing 477
ADC integral nonlinearity (AD21c) INL -11.3 11.3 LSb AVSS = 0V, AVDD = 3.3V 491
ADC differential nonlinearity (AD22c) DNL -1.5 11.5 LSb AVSS = 0V, AVDD = 3.3V 491
ADC gain error (AD23c) GERR -12 12 LSb AVSS = 0V, AVDD = 3.3V 491
ADC offset error (AD24c) EOFF -7.5 7.5 LSb AVSS = 0V, AVDD = 3.3V 491
Thermal resistance, junction to ambient, 48-Pin TQFP 7x7 mm JA 62.76 °C/W 48-Pin TQFP 7x7 mm 466

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PPS bit 10-8 CLKSEL[2:0]: CCPx Time Base Clock Select bits 111 = PPS TxCK input 356

CAD (KiCad official)

  • Symbol: dsPIC33CK64MP105-I
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: dspic33ck64mp105-i-pt-etched.step / dspic33ck64mp105-i-pt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dspic33ck64mp105-i-pt.step / dspic33ck64mp105-i-pt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (530 pp, sha256 5caa91a9637814d2, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF