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DSPIC33CK256MC506-E/PT

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Microchip Tech Digital Signal Processors / Controllers (DSPs/DSCs), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollerdspic33ck256mc506-efactory-2.0.0extractor-text

Verified DSPIC33CK256MC506-E/PT

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DSPIC33CK256MC506-E/PT · TQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 984-page datasheet
  • ✓distributor: lcsc C7171896, digikey 150-DSPIC33CK256MC506-E/PT-ND, mouser 494-33CK256MC506EPT
  • ✓family: TQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-rs5et8i0/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.977)
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 74 kB, viewers/symbol.html 43 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dspic33ck256mc506-e-pt.kicad_sym✓ dspic33ck256mc506-e-pt.kicad_mod✓ dspic33ck256mc506-e-pt.step
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viewers dspic33ck256mc506-e-pt: viewers rendered from the public page · Ray
dspic33ck256mc506-e-pt-etched.glb dspic33ck256mc506-e-pt: factory component page (tier=mfr) · Ray
dspic33ck256mc506-e-pt-etched.step dspic33ck256mc506-e-pt: factory component page (tier=mfr) · Ray
dspic33ck256mc506-e-pt-hero.glb dspic33ck256mc506-e-pt: hero GLB from the etched model (keeps the MPN mark) · Ray
dspic33ck256mc506-e-pt-hero.overlay.json dspic33ck256mc506-e-pt: hero GLB from the etched model (keeps the MPN mark) · Ray
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verification.json Verified: Published by the parts factory: tier mfr, 64 pins · Ray

DSPIC33CK256MC506-E

Microchip Tech · Digital Signal Processors / Controllers (DSPs/DSCs) · TQFP-64(10x10)

DSPIC33CK256MC506-E from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RP46/PWM1H/RB14 bidirectional PORTB bit RB14 I/O with Schmitt Trigger input, also PPS-remappable as RP46 and usable as the PWM1H high-side PWM output.
2 RP47/PWM1L/RB15 bidirectional PORTB bit RB15 I/O with Schmitt Trigger input, also PPS-remappable as RP47 and usable as the PWM1L low-side PWM output.
3 RP60/RC12 bidirectional PORTC bit RC12 I/O with Schmitt Trigger input, also PPS-remappable as RP60.
4 RP61/RC13 bidirectional PORTC bit RC13 I/O with Schmitt Trigger input, also PPS-remappable as RP61.
5 RP62/RC14 bidirectional PORTC bit RC14 I/O with Schmitt Trigger input, also PPS-remappable as RP62.
6 RP63/RC15 bidirectional PORTC bit RC15 I/O with Schmitt Trigger input, also PPS-remappable as RP63.
7 MCLR input Master Clear (Reset) input; active-low Reset to the device, with Schmitt Trigger input.
8 RP79/PCI22/RD15 bidirectional PORTD bit RD15 I/O with Schmitt Trigger input, also PPS-remappable as RP79 and usable as PWM input PCI22.
9 VSS power_in Ground reference for logic and I/O pins; must be connected at all times.
10 VDD power_in Positive supply for peripheral logic and I/O pins; must be connected at all times.
11 RP78/PCI21/RD14 bidirectional PORTD bit RD14 I/O with Schmitt Trigger input, also PPS-remappable as RP78 and usable as PWM input PCI21.
12 ANN0/RP77/RD13 bidirectional PORTD bit RD13 I/O, also analog negative input ANN0 and PPS-remappable as RP77.
13 AN12/RP48/RC0 bidirectional PORTC bit RC0 I/O, also analog input AN12 and PPS-remappable as RP48; analog function is enabled by default after Reset.
14 OA1OUT/AN0/CMP1A/IBIAS0/RA0 bidirectional PORTA bit RA0 I/O, also Op Amp 1 output, analog input AN0, comparator 1A input and 50 µA constant-current output IBIAS0.
15 OA1IN-/AN16/RA1 bidirectional PORTA bit RA1 I/O, also Op Amp 1 inverting input and analog input AN16.
16 OA1IN+/AN9/RA2 bidirectional PORTA bit RA2 I/O, also Op Amp 1 non-inverting input and analog input AN9.
17 DACOUT/AN3/CMP1C/RA3 bidirectional PORTA bit RA3 I/O, also DAC output voltage, analog input AN3 and comparator 1C input.
18 OA3OUT/AN4/IBIAS3/RA4 bidirectional PORTA bit RA4 I/O, also Op Amp 3 output, analog input AN4 and 50 µA constant-current output IBIAS3.
19 AVDD power_in Positive supply for analog modules; must be connected at all times.
20 AVSS power_in Ground reference for analog modules; must be connected at all times.
21 RP76/RD12 bidirectional PORTD bit RD12 I/O with Schmitt Trigger input, also PPS-remappable as RP76.
22 OA3IN-/AN13/CMP1B/ISRC0/RP49/RC1 bidirectional PORTC bit RC1 I/O, also Op Amp 3 inverting input, analog input AN13, comparator 1B input, 10 µA constant-current output ISRC0 and PPS-remappable as RP49.
23 OA3IN+/AN14/CMP2B/ISRC1/RP50/RC2 bidirectional PORTC bit RC2 I/O, also Op Amp 3 non-inverting input, analog input AN14, comparator 2B input, 10 µA constant-current output ISRC1 and PPS-remappable as RP50.
24 AN19/IBIAS1/RP54/RC6 bidirectional PORTC bit RC6 I/O, also analog input AN19, 50 µA constant-current output IBIAS1 and PPS-remappable as RP54.
25 VDD power_in Positive supply for peripheral logic and I/O pins; must be connected at all times.
26 VSS power_in Ground reference for logic and I/O pins; must be connected at all times.
27 AN15/CMP2A/IBIAS2/RP51/RC3 bidirectional PORTC bit RC3 I/O, also analog input AN15, comparator 2A input, 50 µA constant-current output IBIAS2 and PPS-remappable as RP51.
28 OSCI/CLKI/AN5/RP32/RB0 bidirectional Primary oscillator crystal input or external clock input CLKI (ST buffer in RC mode, CMOS otherwise), also PORTB bit RB0, analog input AN5 and PPS-remappable as RP32.
29 OSCO/CLKO/AN6/RP33/RB1(2,4) bidirectional Oscillator crystal output or CLKO output, also PORTB bit RB1 with increased current drive strength (see Electrical Characteristics), analog input AN6 and PPS-remappable as RP33; toggled during programming.
30 CMP2C/RP75/RD11 bidirectional PORTD bit RD11 I/O, also comparator 2C input and PPS-remappable as RP75.
31 AN18/ISRC3/RP74/RD10 bidirectional PORTD bit RD10 I/O, also analog input AN18, 10 µA constant-current output ISRC3 and PPS-remappable as RP74.
32 AN7/ISRC2/RP55/RC7 bidirectional PORTC bit RC7 I/O, also analog input AN7, 10 µA constant-current output ISRC2 and PPS-remappable as RP55.
33 OA2OUT/AN1/CMP1D/CMP2D/RP34/INT0/RB2 bidirectional PORTB bit RB2 I/O, also Op Amp 2 output, analog input AN1, comparator 1D/2D inputs, external interrupt INT0 and PPS-remappable as RP34.
34 PGD2/OA2IN-/AN8/RP35/RB3 bidirectional PORTB bit RB3 I/O, also ICSP/debug data I/O for Communication Channel 2 (PGD2), Op Amp 2 inverting input, analog input AN8 and PPS-remappable as RP35.
35 PGC2/OA2IN+/AN17/RP36/RB4 bidirectional PORTB bit RB4 I/O, also ICSP/debug clock input for Communication Channel 2 (PGC2), Op Amp 2 non-inverting input, analog input AN17 and PPS-remappable as RP36.
36 RP56/ASDA1/SCK2/RC8(2) bidirectional PORTC bit RC8 I/O with increased current drive strength, also alternate I2C1 data ASDA1, SPI2 clock SCK2 and PPS-remappable as RP56.
37 RP57/ASCL1/SDI2/RC9(2) bidirectional PORTC bit RC9 I/O with increased current drive strength, also alternate I2C1 clock ASCL1, SPI2 data input SDI2 and PPS-remappable as RP57.
38 RP73/PCI20/RD9 bidirectional PORTD bit RD9 I/O, also PPS-remappable as RP73 and usable as PWM input PCI20.
39 RP72/SDO2/PCI19/RD8(2) bidirectional PORTD bit RD8 I/O with increased current drive strength, also SPI2 data output SDO2, PWM input PCI19 and PPS-remappable as RP72.
40 VSS power_in Ground reference for logic and I/O pins; must be connected at all times.
41 VDD power_in Positive supply for peripheral logic and I/O pins; must be connected at all times.
42 RP71/RD7 bidirectional PORTD bit RD7 I/O, also PPS-remappable as RP71.
43 RP70/RD6 bidirectional PORTD bit RD6 I/O, also PPS-remappable as RP70.
44 RP69/RD5 bidirectional PORTD bit RD5 I/O, also PPS-remappable as RP69.
45 PGD3/RP37/RB5 bidirectional PORTB bit RB5 I/O, also ICSP/debug data I/O for Communication Channel 3 (PGD3) and PPS-remappable as RP37.
46 PGC3/RP38/RB6 bidirectional PORTB bit RB6 I/O, also ICSP/debug clock input for Communication Channel 3 (PGC3) and PPS-remappable as RP38.
47 TDO/AN2/RP39/RB7 bidirectional PORTB bit RB7 I/O, also JTAG test data output TDO, analog input AN2 and PPS-remappable as RP39.
48 PGD1/AN10/RP40/SCL1/RB8 bidirectional PORTB bit RB8 I/O, also ICSP/debug data I/O for Communication Channel 1 (PGD1), analog input AN10, I2C1 clock SCL1 and PPS-remappable as RP40.
49 PGC1/AN11/RP41/SDA1/RB9 bidirectional PORTB bit RB9 I/O, also ICSP/debug clock input for Communication Channel 1 (PGC1), analog input AN11, I2C1 data SDA1 and PPS-remappable as RP41.
50 RP52/RC4 bidirectional PORTC bit RC4 I/O, also PPS-remappable as RP52.
51 RP53/RC5 bidirectional PORTC bit RC5 I/O, also PPS-remappable as RP53.
52 RP58/RC10 bidirectional PORTC bit RC10 I/O, also PPS-remappable as RP58.
53 RP59/RC11 bidirectional PORTC bit RC11 I/O, also PPS-remappable as RP59.
54 RP68/RD4 bidirectional PORTD bit RD4 I/O, also PPS-remappable as RP68.
55 RP67/RD3 bidirectional PORTD bit RD3 I/O, also PPS-remappable as RP67.
56 VSS power_in Ground reference for logic and I/O pins; must be connected at all times.
57 VDD power_in Positive supply for peripheral logic and I/O pins; must be connected at all times.
58 RP66/RD2 bidirectional PORTD bit RD2 I/O, also PPS-remappable as RP66.
59 RP65/PWM4H/RD1 bidirectional PORTD bit RD1 I/O, also PPS-remappable as RP65 and usable as the PWM4H high-side PWM output.
60 RP64/PWL4L/RD0 bidirectional PORTD bit RD0 I/O, also PPS-remappable as RP64 and carrying the PWM low output named 'PWL4L' as printed in the datasheet.
61 TMS/RP42/PWM3H/RB10(3) bidirectional JTAG test mode select input TMS, also PORTB bit RB10, PWM3H high output and PPS-remappable as RP42; a pull-up during programming or JTAG limits this pin to 3.6 V, and it can reach 5.5 V only if JTAG is disabled.
62 TCK/RP43/PWM3L/RB11 bidirectional JTAG test clock input TCK, also PORTB bit RB11, PWM3L low output and PPS-remappable as RP43.
63 TDI/RP44/PWM2H/RB12 bidirectional JTAG test data input TDI, also PORTB bit RB12, PWM2H high output and PPS-remappable as RP44.
64 RP45/PWM2L/RB13 bidirectional PORTB bit RB13 I/O, also PWM2L low output and PPS-remappable as RP45.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-64(10x10)
Category Single Chip Microcomputer/Microcontroller
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -40 125 °C 917
Storage temperature -65 150 °C 917
Voltage on VDD with respect to VSS VDD -0.3 4 V 917
Voltage on any pin that is not 5V tolerant with respect to VSS -0.3 V Upper limit printed as VDD + 0.3V 917
Voltage on any 5V tolerant pin with respect to VSS -0.3 5.5 V 917
Maximum current out of VSS pin 300 mA 917
Maximum current into VDD pin 300 mA 917
Maximum current sunk/sourced by any regular I/O pin 15 mA 917
Maximum current sunk/sourced by I/O pin with increased current drive strength 25 mA RB1, RC8, RC9 and RD8 pins 917
Maximum current sunk by a group of I/Os between two VSS pins 75 mA Not applicable to AVDD and AVSS 917
Maximum current sourced by a group of I/Os between two VDD pins 75 mA Not applicable to AVDD and AVSS 917
Maximum current sunk by all I/Os 200 mA 917
Maximum current sourced by all I/Os 200 mA 917
Supply voltage VDD VDD 3 3.6 V 919
Maximum CPU clock frequency 100 MHz VDD 3.0V to 3.6V, -40°C to +125°C 917
Operating junction temperature range (extended temperature devices) TJ -40 140 °C Extended temperature devices 918
Operating ambient temperature range (extended temperature devices) TA -40 125 °C Extended temperature devices 918
Supply voltage AVDD AVDD 3 3.6 V AVDD greater of VDD-0.3 or 3.0 and lesser of VDD+0.3 or 3.6; AVDD and VDD difference must not exceed ±300 mV 919
VDD rise rate to ensure internal power-on reset signal SVDD 0.03 V/ms 0V-3V in 100 ms 919
BOR event on VDD transition high-to-low VBOR 2.68 2.99 V Design guidance only, not tested in manufacturing 919
Operating current (IDD) DC20 IDD 9 22 mA +125°C 3.3V 10 MIPS (N = 1, N2 = 5, N3 = 2, M = 50, FVCO = 400 MHz, FPLLO = 40 MHz) 919
Operating current (IDD) DC21 IDD 10.7 25 mA +125°C 3.3V 20 MIPS (N = 1, N2 = 5, N3 = 1, M = 60, FVCO = 480 MHz, FPLLO = 280 MHz) 919
Operating current (IDD) DC22 IDD 14.5 28 mA +125°C 3.3V 40 MIPS (N = 1, N2 = 3, N3 = 1, M = 60, FVCO = 480 MHz, FPLLO = 160 MHz) 919
Operating current (IDD) DC23 IDD 20 35 mA +125°C 3.3V 70 MIPS (N = 1, N2 = 2, N3 = 1, M = 70, FVCO = 560 MHz, FPLLO = 280 MHz) 919
Operating current (IDD) DC24 IDD 23.5 35 mA +125°C 3.3V 90 MIPS (N = 1, N2 = 2, N3 = 1, M = 90, FVCO = 720 MHz, FPLLO = 360 MHz) 920
Operating current (IDD) DC25 IDD 23 38 mA +125°C 3.3V 100 MIPS (N = 1, N2 = 1, N3 = 1, M = 50, FVCO = 400 MHz, FPLLO = 400 MHz) 920
Idle current (IIDLE) DC30 IIDLE 7.7 20 mA +125°C 3.3V 10 MIPS (N = 1, N2 = 5, N3 = 2, M = 50, FVCO = 400 MHz, FPLLO = 40 MHz) 920
Idle current (IIDLE) DC31 IIDLE 8.2 20 mA +125°C 3.3V 20 MIPS (N = 1, N2 = 5, N3 = 1, M = 50, FVCO = 400 MHz, FPLLO = 80 MHz) 920
Idle current (IIDLE) DC32 IIDLE 9.7 22 mA +125°C 3.3V 40 MIPS (N = 1, N2 = 3, N3 = 1, M = 60, FVCO = 480 MHz, FPLLO = 160 MHz) 920
Idle current (IIDLE) DC33 IIDLE 11.8 25 mA +125°C 3.3V 70 MIPS (N = 1, N2 = 2, N3 = 1, M = 70, FVCO = 660 MHz, FPLLO = 280 MHz) 921
Idle current (IIDLE) DC34 IIDLE 13.8 26 mA +125°C 3.3V 90 MIPS (N = 1, N2 = 2, N3 = 1, M = 90, FVCO = 720 MHz, FPLLO = 360 MHz) 921
Idle current (IIDLE) DC35 IIDLE 12.2 28 mA +125°C 3.3V 100 MIPS (N = 1, N2 = 1, N3 = 1, M = 50, FVCO = 400 MHz, FPLLO = 400 MHz) 921
Power-down current (IPD) DC40 IPD 0.285 0.7 mA -40°C 3.3V VREGS bit (RCON[8]) = 0, LPWREN bit (VREGCON[15]) = 1 922
Power-down current (IPD) DC40 IPD 0.32 1 mA +25°C 3.3V VREGS bit (RCON[8]) = 0, LPWREN bit (VREGCON[15]) = 1 922
Power-down current (IPD) DC40 IPD 1500 5 mA +85°C 3.3V VREGS bit (RCON[8]) = 0, LPWREN bit (VREGCON[15]) = 1 922
Power-down current (IPD) DC41 IPD 4.5 15 mA +125°C 3.3V VREGS bit (RCON[8]) = 1, LPWREN bit (VREGCON[15]) = 0 (regulators in High-Power mode) 922
Input pull-up current with pull-up enabled (DI30) ICNPU 175 545 µA VDD = 3.3V, VPIN = VSS 925
Input pull-down current with pull-down enabled (DI31) ICNPD 65 360 µA VDD = 3.3V, VPIN = VDD 925
Input leakage current I/O pins and MCLR (DI50) IIL -700 nA VPIN = VSS 925
Input leakage current I/O pins and MCLR (DI50) IIL 700 nA VPIN = VDD 925
INTx input pins high or low time (DI35) TINP 20 ns 928
I/O and CNx inputs high or low time (DI40) TRPB 2 TCY 928
Port output rise time (DO31) TIOR 10 ns Characterized, not tested in manufacturing 928
Port output fall time (DO32) TIOF 10 ns Characterized, not tested in manufacturing 928
Total input injection current, sum of all I/O and control pins (DI60c) ΣLICT -20 20 mA Absolute instantaneous sum of all ± input injection currents from all I/O pins 926
Program Flash cell endurance (D130) EP 10000 E/W 927
Program Flash characteristic retention (D134) TRETD 20 Year 927
Self-timed page erase time (D137a) TPE 20 ms 927
Self-timed chip erase time (D137b) TCE 20 ms 927
Self-timed double-word write cycle time (D138a) TWW 20 µs 6 bytes, data are not all '1's 927
Self-timed row write cycle time (D138b) TRW 1.28 ms 384 bytes, data are not all '1's 927
External CLKI frequency (OS10) FIN 64 MHz EC 929
Crystal oscillator frequency (OS10) FIN 3.5 10 MHz XT 929
Oscillator frequency (OS10) FIN 10 32 MHz HS 929
External clock in (OSCI) rise or fall time (OS31) TOSR,TOSF 10 ns EC; characterized, not tested in manufacturing 929
PLL input frequency range (OS50) FPLLI 8 64 MHz 929
VCO output frequency (OS52) FVCO 400 1600 MHz 929
Lock time for PLL (OS53) TLOCK 250 µS Characterized, not tested in manufacturing 929
Junction to ambient thermal resistance, 64-Pin TQFP 10x10x1.0 mm θJA 45.7 °C/W Package simulation 918

CAD (KiCad official)

  • Symbol: DSPIC33CK256MC506-E
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: dspic33ck256mc506-e-pt-etched.step / dspic33ck256mc506-e-pt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dspic33ck256mc506-e-pt.step / dspic33ck256mc506-e-pt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (984 pp, sha256 49806b12be64e196, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF