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DSPIC33CH512MP208-I
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Microchip Tech Pre-ordered MCUs, TQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DSPIC33CH512MP208-I
Microchip Tech · Pre-ordered MCUs · TQFP-80(12x12)
DSPIC33CH512MP208-I from Microchip Tech, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RP46/PWM1H/RB14 | bidirectional | Master core function is RP46/PWM1H/RB14 (remappable I/O RP46, PWM1H output, port RB14); slave core alternates are S1RP46/S1RB14. |
| 2 | RE0 | bidirectional | Master core function is port pin RE0; slave core alternate is S1RE0. |
| 3 | RP47/PWM1L/RB15 | bidirectional | Master core function is RP47/PWM1L/RB15 (remappable I/O RP47, PWM1L output, port RB15); slave core alternates are S1RP47/S1RB15. |
| 4 | RE1 | bidirectional | Master core function is port pin RE1; slave core alternate is S1RE1. |
| 5 | RP60/PWM4H/RC12 | bidirectional | Master core function is RP60/PWM4H/RC12 (remappable I/O RP60, PWM4H output, port RC12); slave core alternates are S1RP60/S1RC12. |
| 6 | RP61/PWM4L/RC13 | bidirectional | Master core function is RP61/PWM4L/RC13 (remappable I/O RP61, PWM4L output, port RC13); slave core alternates are S1RP61/S1RC13. |
| 7 | RP62/RC14 | bidirectional | Master core function is RP62/RC14 (remappable I/O RP62, port RC14); slave core alternates are S1RP62/S1PWM7H/S1RC14. |
| 8 | RP63/RC15 | bidirectional | Master core function is RP63/RC15 (remappable I/O RP63, port RC15); slave core alternates are S1RP63/S1PWM7L/S1RC15. |
| 9 | MCLR | input | Master clear (device reset) input shared by the master and slave cores. |
| 10 | PCI22/RD15 | bidirectional | Master core function is PCI22/RD15 (peripheral change input PCI22, port RD15); slave core alternates are S1PCI22/S1RD15. |
| 11 | VSS | power_in | Digital ground pin. |
| 12 | VDD | power_in | Digital supply pin; the datasheet headline operating range is 3V to 3.6V. |
| 13 | PCI21/RD14 | bidirectional | Master core function is PCI21/RD14 (peripheral change input PCI21, port RD14); slave core alternates are S1ANN1/S1PGA2N2/S1PCI21/S1RD14. |
| 14 | RD13 | bidirectional | Master core function is port pin RD13; slave core alternates are S1ANN0/S1PGA1N2/S1RD13. |
| 15 | AN12/IBIAS3/RP48/RC0 | bidirectional | Master core function is AN12/IBIAS3/RP48/RC0 (ADC channel AN12, current bias IBIAS3, remappable RP48, port RC0); slave core alternates are S1AN10/S1RP48/S1RC0. |
| 16 | AN0/CMP1A/RA0 | bidirectional | Master core function is AN0/CMP1A/RA0 (ADC channel AN0, comparator 1 input CMP1A, port RA0); slave core alternate is S1RA0. |
| 17 | RE2 | bidirectional | Master core function is port pin RE2; slave core alternate is S1RE2. |
| 18 | AN1/RA1 | bidirectional | Master core function is AN1/RA1 (ADC channel AN1, port RA1); slave core alternates are S1AN15/S1RA1. |
| 19 | RE3 | bidirectional | Master core function is port pin RE3; slave core alternate is S1RE3. |
| 20 | AN2/RA2 | bidirectional | Master core function is AN2/RA2 (ADC channel AN2, port RA2); slave core alternates are S1AN16/S1RA2. |
| 21 | AN3/IBIAS0/RA3 | bidirectional | Master core function is AN3/IBIAS0/RA3 (ADC channel AN3, current bias IBIAS0, port RA3); slave core alternates are S1AN0/S1CMP1A/S1PGA1P1/S1RA3. |
| 22 | RE4 | bidirectional | Master core function is port pin RE4; slave core alternate is S1RE4. |
| 23 | AN4/IBIAS1/RA4 | bidirectional | Master core function is AN4/IBIAS1/RA4 (ADC channel AN4, current bias IBIAS1, port RA4); slave core alternates are S1MCLR3/S1AN1/S1CMP2A/S1PGA2P1/S1PGA3P2/S1RA4. |
| 24 | RE5 | bidirectional | Master core function is port pin RE5; slave core alternate is S1RE5. |
| 25 | AVDD | power_in | Analog supply pin. |
| 26 | AVSS | power_in | Analog ground pin. |
| 27 | RD12 | bidirectional | Master core function is port pin RD12; slave core alternates are S1AN14/S1PGA2P2/S1RD12. |
| 28 | AN13/ISRC0/RP49/RC1 | bidirectional | Master core function is AN13/ISRC0/RP49/RC1 (ADC channel AN13, current source ISRC0, remappable RP49, port RC1); slave core alternates are S1ANA1/S1RP49/S1RC1. |
| 29 | AN14/ISRC1/RP50/RC2 | bidirectional | Master core function is AN14/ISRC1/RP50/RC2 (ADC channel AN14, current source ISRC1, remappable RP50, port RC2); slave core alternates are S1ANA0/S1RP50/S1RC2. |
| 30 | RP54/RC6 | bidirectional | Master core function is RP54/RC6 (remappable I/O RP54, port RC6); slave core alternates are S1AN11/S1CMP1B/S1RP54/S1RC6. |
| 31 | VDD | power_in | Digital supply pin; the datasheet headline operating range is 3V to 3.6V. |
| 32 | VSS | power_in | Digital ground pin. |
| 33 | CMP1B/RP51/RC3 | bidirectional | Master core function is CMP1B/RP51/RC3 (comparator 1 input CMP1B, remappable RP51, port RC3); slave core alternates are S1AN8/S1CMP3B/S1RP51/S1RC3. |
| 34 | OSCI/CLKI/AN5/RP32/RB0 | input | Oscillator input pin (OSCI/CLKI), also ADC channel AN5, remappable RP32 and port RB0; slave core alternates are S1AN5/S1RP32/S1RB0. |
| 35 | OSCO/CLKO/AN6/IBIAS2/RP33/RB1 | output | Oscillator output pin (OSCO/CLKO), also ADC channel AN6, current bias IBIAS2, remappable RP33 and port RB1; slave core alternates are S1AN4/S1RP33/S1RB1. |
| 36 | RD11 | bidirectional | Master core function is port pin RD11; slave core alternates are S1AN17/S1PGA1P2/S1RD11. |
| 37 | RE6 | bidirectional | Master core function is port pin RE6; slave core alternates are S1PGA3N2/S1RE6. |
| 38 | ISRC3/RD10 | bidirectional | Master core function is ISRC3/RD10 (current source ISRC3, port RD10); slave core alternates are S1AN13/S1CMP2B/S1RD10. |
| 39 | RE7 | bidirectional | Master core function is port pin RE7; slave core alternate is S1RE7. |
| 40 | AN15/ISRC2/RP55/RC7 | bidirectional | Master core function is AN15/ISRC2/RP55/RC7 (ADC channel AN15, current source ISRC2, remappable RP55, port RC7); slave core alternates are S1AN12/S1RP55/S1RC7. |
| 41 | DACOUT/AN7/CMP1D/RP34/INT0/RB2 | bidirectional | Master core function is DACOUT/AN7/CMP1D/RP34/INT0/RB2 (DAC output, ADC channel AN7, comparator 1 input CMP1D, remappable RP34, external interrupt INT0, port RB2); multiple slave core alternates are listed in Table 6. |
| 42 | RE8 | bidirectional | Master core function is port pin RE8; slave core alternate is S1RE8. |
| 43 | PGD2/AN8/RP35/RB3 | bidirectional | Master core function is PGD2/AN8/RP35/RB3 (programming/debug data PGD2, ADC channel AN8, remappable RP35, port RB3); slave core alternates are S1PGD2/S1AN18/S1CMP3A/S1PGA3P1/S1RP35/S1RB3. |
| 44 | RE9 | bidirectional | Master core function is port pin RE9; slave core alternate is S1RE9. |
| 45 | PGC2/RP36/RB4 | input | Master core function is PGC2/RP36/RB4 (programming/debug clock PGC2, remappable RP36, port RB4); slave core alternates are S1PGC2/S1AN9/S1RP36/S1PWM5L/S1RB4. |
| 46 | RP56/ASDA1/SCK2/RC8 | bidirectional | Master core function is RP56/ASDA1/SCK2/RC8 (remappable RP56, alternate serial data ASDA1, SPI2 clock SCK2, port RC8); slave core alternates are S1RP56/S1ASDA1/S1SCK1/S1RC8. |
| 47 | RP57/ASCL1/SDI2/RC9 | bidirectional | Master core function is RP57/ASCL1/SDI2/RC9 (remappable RP57, alternate serial clock ASCL1, SPI2 data input SDI2, port RC9); slave core alternates are S1RP57/S1ASCL1/S1SDI1/S1RC9. |
| 48 | PCI20/RD9 | bidirectional | Master core function is PCI20/RD9 (peripheral change input PCI20, port RD9); slave core alternates are S1PCI20/S1RD9. |
| 49 | SDO2/PCI19/RD8 | bidirectional | Master core function is SDO2/PCI19/RD8 (SPI2 data output SDO2, peripheral change input PCI19, port RD8); slave core alternates are S1SDO1/S1PCI19/S1RD8. |
| 50 | VSS | power_in | Digital ground pin. |
| 51 | VDD | power_in | Digital supply pin; the datasheet headline operating range is 3V to 3.6V. |
| 52 | RP71/RD7 | bidirectional | Master core function is RP71/RD7 (remappable I/O RP71, port RD7); slave core alternates are S1RP71/S1PWM8H/S1RD7. |
| 53 | RP70/RD6 | bidirectional | Master core function is RP70/RD6 (remappable I/O RP70, port RD6); slave core alternates are S1RP70/S1PWM6H/S1RD6. |
| 54 | RP69/RD5 | bidirectional | Master core function is RP69/RD5 (remappable I/O RP69, port RD5); slave core alternates are S1RP69/S1PWM6L/S1RD5. |
| 55 | PGD3/RP37/SDA2/RB5 | bidirectional | Master core function is PGD3/RP37/SDA2/RB5 (programming/debug data PGD3, remappable RP37, I2C2 data SDA2, port RB5); slave core alternates are S1PGD3/S1RP37/S1RB5. |
| 56 | PGC3/RP38/SCL2/RB6 | input | Master core function is PGC3/RP38/SCL2/RB6 (programming/debug clock PGC3, remappable RP38, I2C2 clock SCL2, port RB6); slave core alternates are S1PGC3/S1RP38/S1RB6. |
| 57 | RE10 | bidirectional | Master core function is port pin RE10; slave core alternate is S1RE10. |
| 58 | TDO/AN9/RP39/RB7 | bidirectional | Master core function is TDO/AN9/RP39/RB7 (JTAG data output TDO, ADC channel AN9, remappable RP39, port RB7); slave core alternates are S1MCLR1/S1AN6/S1RP39/S1PWM5H/S1RB7. |
| 59 | RE11 | bidirectional | Master core function is port pin RE11; slave core alternate is S1RE11. |
| 60 | PGD1/AN10/RP40/SCL1/RB8 | bidirectional | Master core function is PGD1/AN10/RP40/SCL1/RB8 (programming/debug data PGD1, ADC channel AN10, remappable RP40, I2C1 clock SCL1, port RB8); slave core alternates are S1PGD1/S1AN7/S1RP40/S1SCL1/S1RB8. |
| 61 | PGC1/AN11/RP41/SDA1/RB9 | input | Master core function is PGC1/AN11/RP41/SDA1/RB9 (programming/debug clock PGC1, ADC channel AN11, remappable RP41, I2C1 data SDA1, port RB9); slave core alternates are S1PGC1/S1RP41/S1SDA1/S1RB9. |
| 62 | ASCL2/RE12 | bidirectional | Master core function is alternate serial clock ASCL2 on port RE12; slave core alternate is S1RE12. |
| 63 | RP52/RC4 | bidirectional | Master core function is RP52/RC4 (remappable I/O RP52, port RC4); slave core alternates are S1RP52/S1PWM2H/S1RC4. |
| 64 | ASDA2/RE13 | bidirectional | Master core function is alternate serial data ASDA2 on port RE13; slave core alternate is S1RE13. |
| 65 | RP53/RC5 | bidirectional | Master core function is RP53/RC5 (remappable I/O RP53, port RC5); slave core alternates are S1RP53/S1PWM2L/S1RC5. |
| 66 | RP58/RC10 | bidirectional | Master core function is RP58/RC10 (remappable I/O RP58, port RC10); slave core alternates are S1RP58/S1PWM1H/S1RC10. |
| 67 | RP59/RC11 | bidirectional | Master core function is RP59/RC11 (remappable I/O RP59, port RC11); slave core alternates are S1RP59/S1PWM1L/S1RC11. |
| 68 | RP68/RD4 | bidirectional | Master core function is RP68/RD4 (remappable I/O RP68, port RD4); slave core alternates are S1RP68/S1PWM3H/S1RD4. |
| 69 | RP67/RD3 | bidirectional | Master core function is RP67/RD3 (remappable I/O RP67, port RD3); slave core alternates are S1RP67/S1PWM3L/S1RD3. |
| 70 | VSS | power_in | Digital ground pin. |
| 71 | VDD | power_in | Digital supply pin; the datasheet headline operating range is 3V to 3.6V. |
| 72 | RP66/RD2 | bidirectional | Master core function is RP66/RD2 (remappable I/O RP66, port RD2); slave core alternates are S1RP66/S1PWM8L/S1RD2. |
| 73 | RP65/RD1 | bidirectional | Master core function is RP65/RD1 (remappable I/O RP65, port RD1); slave core alternates are S1RP65/S1PWM4H/S1RD1. |
| 74 | RP64/RD0 | bidirectional | Master core function is RP64/RD0 (remappable I/O RP64, port RD0); slave core alternates are S1RP64/S1PWM4L/S1RD0. |
| 75 | TMS/RP42/PWM3H/RB10 | bidirectional | Master core function is TMS/RP42/PWM3H/RB10 (JTAG mode select TMS, remappable RP42, PWM3H output, port RB10); slave core alternates are S1RP42/S1RB10. |
| 76 | TCK/RP43/PWM3L/RB11 | bidirectional | Master core function is TCK/RP43/PWM3L/RB11 (JTAG clock TCK, remappable RP43, PWM3L output, port RB11); slave core alternates are S1RP43/S1RB11. |
| 77 | RE14 | bidirectional | Master core function is port pin RE14; slave core alternate is S1RE14. |
| 78 | TDI/RP44/PWM2H/RB12 | bidirectional | Master core function is TDI/RP44/PWM2H/RB12 (JTAG data input TDI, remappable RP44, PWM2H output, port RB12); slave core alternates are S1RP44/S1RB12. |
| 79 | RE15 | bidirectional | Master core function is port pin RE15; slave core alternate is S1RE15. |
| 80 | RP45/PWM2L/RB13 | bidirectional | Master core function is RP45/PWM2L/RB13 (remappable I/O RP45, PWM2L output, port RB13); slave core alternates are S1RP45/S1RB13. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-80(12x12) |
| Category | Embedded Processors & Controllers |
| Pins | 80 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating voltage (family headline, Operating Conditions bullet) | 3 | 3.6 | V | 1 |
CAD (KiCad official)
- Symbol:
DSPIC33CH512MP208-I - Footprint:
Package_QFP:TQFP-80_12x12mm_P0.5mm - 3D model: TQFP-80(12x12) (KiCad packages3D, STEP)
- 3D model files:
dspic33ch512mp208-i-etched.step/dspic33ch512mp208-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dspic33ch512mp208-i.step/dspic33ch512mp208-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (16 pp, sha256
856e174c082eba86, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DSPIC33CH512MP208-I
**Microchip Tech** · Pre-ordered MCUs · TQFP-80(12x12)
DSPIC33CH512MP208-I from Microchip Tech, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RP46/PWM1H/RB14 | bidirectional | Master core function is RP46/PWM1H/RB14 (remappable I/O RP46, PWM1H output, port RB14); slave core alternates are S1RP46/S1RB14. |
| 2 | RE0 | bidirectional | Master core function is port pin RE0; slave core alternate is S1RE0. |
| 3 | RP47/PWM1L/RB15 | bidirectional | Master core function is RP47/PWM1L/RB15 (remappable I/O RP47, PWM1L output, port RB15); slave core alternates are S1RP47/S1RB15. |
| 4 | RE1 | bidirectional | Master core function is port pin RE1; slave core alternate is S1RE1. |
| 5 | RP60/PWM4H/RC12 | bidirectional | Master core function is RP60/PWM4H/RC12 (remappable I/O RP60, PWM4H output, port RC12); slave core alternates are S1RP60/S1RC12. |
| 6 | RP61/PWM4L/RC13 | bidirectional | Master core function is RP61/PWM4L/RC13 (remappable I/O RP61, PWM4L output, port RC13); slave core alternates are S1RP61/S1RC13. |
| 7 | RP62/RC14 | bidirectional | Master core function is RP62/RC14 (remappable I/O RP62, port RC14); slave core alternates are S1RP62/S1PWM7H/S1RC14. |
| 8 | RP63/RC15 | bidirectional | Master core function is RP63/RC15 (remappable I/O RP63, port RC15); slave core alternates are S1RP63/S1PWM7L/S1RC15. |
| 9 | MCLR | input | Master clear (device reset) input shared by the master and slave cores. |
| 10 | PCI22/RD15 | bidirectional | Master core function is PCI22/RD15 (peripheral change input PCI22, port RD15); slave core alternates are S1PCI22/S1RD15. |
| 11 | VSS | power_in | Digital ground pin. |
| 12 | VDD | power_in | Digital supply pin; the datasheet headline operating range is 3V to 3.6V. |
| 13 | PCI21/RD14 | bidirectional | Master core function is PCI21/RD14 (peripheral change input PCI21, port RD14); slave core alternates are S1ANN1/S1PGA2N2/S1PCI21/S1RD14. |
| 14 | RD13 | bidirectional | Master core function is port pin RD13; slave core alternates are S1ANN0/S1PGA1N2/S1RD13. |
| 15 | AN12/IBIAS3/RP48/RC0 | bidirectional | Master core function is AN12/IBIAS3/RP48/RC0 (ADC channel AN12, current bias IBIAS3, remappable RP48, port RC0); slave core alternates are S1AN10/S1RP48/S1RC0. |
| 16 | AN0/CMP1A/RA0 | bidirectional | Master core function is AN0/CMP1A/RA0 (ADC channel AN0, comparator 1 input CMP1A, port RA0); slave core alternate is S1RA0. |
| 17 | RE2 | bidirectional | Master core function is port pin RE2; slave core alternate is S1RE2. |
| 18 | AN1/RA1 | bidirectional | Master core function is AN1/RA1 (ADC channel AN1, port RA1); slave core alternates are S1AN15/S1RA1. |
| 19 | RE3 | bidirectional | Master core function is port pin RE3; slave core alternate is S1RE3. |
| 20 | AN2/RA2 | bidirectional | Master core function is AN2/RA2 (ADC channel AN2, port RA2); slave core alternates are S1AN16/S1RA2. |
| 21 | AN3/IBIAS0/RA3 | bidirectional | Master core function is AN3/IBIAS0/RA3 (ADC channel AN3, current bias IBIAS0, port RA3); slave core alternates are S1AN0/S1CMP1A/S1PGA1P1/S1RA3. |
| 22 | RE4 | bidirectional | Master core function is port pin RE4; slave core alternate is S1RE4. |
| 23 | AN4/IBIAS1/RA4 | bidirectional | Master core function is AN4/IBIAS1/RA4 (ADC channel AN4, current bias IBIAS1, port RA4); slave core alternates are S1MCLR3/S1AN1/S1CMP2A/S1PGA2P1/S1PGA3P2/S1RA4. |
| 24 | RE5 | bidirectional | Master core function is port pin RE5; slave core alternate is S1RE5. |
| 25 | AVDD | power_in | Analog supply pin. |
| 26 | AVSS | power_in | Analog ground pin. |
| 27 | RD12 | bidirectional | Master core function is port pin RD12; slave core alternates are S1AN14/S1PGA2P2/S1RD12. |
| 28 | AN13/ISRC0/RP49/RC1 | bidirectional | Master core function is AN13/ISRC0/RP49/RC1 (ADC channel AN13, current source ISRC0, remappable RP49, port RC1); slave core alternates are S1ANA1/S1RP49/S1RC1. |
| 29 | AN14/ISRC1/RP50/RC2 | bidirectional | Master core function is AN14/ISRC1/RP50/RC2 (ADC channel AN14, current source ISRC1, remappable RP50, port RC2); slave core alternates are S1ANA0/S1RP50/S1RC2. |
| 30 | RP54/RC6 | bidirectional | Master core function is RP54/RC6 (remappable I/O RP54, port RC6); slave core alternates are S1AN11/S1CMP1B/S1RP54/S1RC6. |
| 31 | VDD | power_in | Digital supply pin; the datasheet headline operating range is 3V to 3.6V. |
| 32 | VSS | power_in | Digital ground pin. |
| 33 | CMP1B/RP51/RC3 | bidirectional | Master core function is CMP1B/RP51/RC3 (comparator 1 input CMP1B, remappable RP51, port RC3); slave core alternates are S1AN8/S1CMP3B/S1RP51/S1RC3. |
| 34 | OSCI/CLKI/AN5/RP32/RB0 | input | Oscillator input pin (OSCI/CLKI), also ADC channel AN5, remappable RP32 and port RB0; slave core alternates are S1AN5/S1RP32/S1RB0. |
| 35 | OSCO/CLKO/AN6/IBIAS2/RP33/RB1 | output | Oscillator output pin (OSCO/CLKO), also ADC channel AN6, current bias IBIAS2, remappable RP33 and port RB1; slave core alternates are S1AN4/S1RP33/S1RB1. |
| 36 | RD11 | bidirectional | Master core function is port pin RD11; slave core alternates are S1AN17/S1PGA1P2/S1RD11. |
| 37 | RE6 | bidirectional | Master core function is port pin RE6; slave core alternates are S1PGA3N2/S1RE6. |
| 38 | ISRC3/RD10 | bidirectional | Master core function is ISRC3/RD10 (current source ISRC3, port RD10); slave core alternates are S1AN13/S1CMP2B/S1RD10. |
| 39 | RE7 | bidirectional | Master core function is port pin RE7; slave core alternate is S1RE7. |
| 40 | AN15/ISRC2/RP55/RC7 | bidirectional | Master core function is AN15/ISRC2/RP55/RC7 (ADC channel AN15, current source ISRC2, remappable RP55, port RC7); slave core alternates are S1AN12/S1RP55/S1RC7. |
| 41 | DACOUT/AN7/CMP1D/RP34/INT0/RB2 | bidirectional | Master core function is DACOUT/AN7/CMP1D/RP34/INT0/RB2 (DAC output, ADC channel AN7, comparator 1 input CMP1D, remappable RP34, external interrupt INT0, port RB2); multiple slave core alternates are listed in Table 6. |
| 42 | RE8 | bidirectional | Master core function is port pin RE8; slave core alternate is S1RE8. |
| 43 | PGD2/AN8/RP35/RB3 | bidirectional | Master core function is PGD2/AN8/RP35/RB3 (programming/debug data PGD2, ADC channel AN8, remappable RP35, port RB3); slave core alternates are S1PGD2/S1AN18/S1CMP3A/S1PGA3P1/S1RP35/S1RB3. |
| 44 | RE9 | bidirectional | Master core function is port pin RE9; slave core alternate is S1RE9. |
| 45 | PGC2/RP36/RB4 | input | Master core function is PGC2/RP36/RB4 (programming/debug clock PGC2, remappable RP36, port RB4); slave core alternates are S1PGC2/S1AN9/S1RP36/S1PWM5L/S1RB4. |
| 46 | RP56/ASDA1/SCK2/RC8 | bidirectional | Master core function is RP56/ASDA1/SCK2/RC8 (remappable RP56, alternate serial data ASDA1, SPI2 clock SCK2, port RC8); slave core alternates are S1RP56/S1ASDA1/S1SCK1/S1RC8. |
| 47 | RP57/ASCL1/SDI2/RC9 | bidirectional | Master core function is RP57/ASCL1/SDI2/RC9 (remappable RP57, alternate serial clock ASCL1, SPI2 data input SDI2, port RC9); slave core alternates are S1RP57/S1ASCL1/S1SDI1/S1RC9. |
| 48 | PCI20/RD9 | bidirectional | Master core function is PCI20/RD9 (peripheral change input PCI20, port RD9); slave core alternates are S1PCI20/S1RD9. |
| 49 | SDO2/PCI19/RD8 | bidirectional | Master core function is SDO2/PCI19/RD8 (SPI2 data output SDO2, peripheral change input PCI19, port RD8); slave core alternates are S1SDO1/S1PCI19/S1RD8. |
| 50 | VSS | power_in | Digital ground pin. |
| 51 | VDD | power_in | Digital supply pin; the datasheet headline operating range is 3V to 3.6V. |
| 52 | RP71/RD7 | bidirectional | Master core function is RP71/RD7 (remappable I/O RP71, port RD7); slave core alternates are S1RP71/S1PWM8H/S1RD7. |
| 53 | RP70/RD6 | bidirectional | Master core function is RP70/RD6 (remappable I/O RP70, port RD6); slave core alternates are S1RP70/S1PWM6H/S1RD6. |
| 54 | RP69/RD5 | bidirectional | Master core function is RP69/RD5 (remappable I/O RP69, port RD5); slave core alternates are S1RP69/S1PWM6L/S1RD5. |
| 55 | PGD3/RP37/SDA2/RB5 | bidirectional | Master core function is PGD3/RP37/SDA2/RB5 (programming/debug data PGD3, remappable RP37, I2C2 data SDA2, port RB5); slave core alternates are S1PGD3/S1RP37/S1RB5. |
| 56 | PGC3/RP38/SCL2/RB6 | input | Master core function is PGC3/RP38/SCL2/RB6 (programming/debug clock PGC3, remappable RP38, I2C2 clock SCL2, port RB6); slave core alternates are S1PGC3/S1RP38/S1RB6. |
| 57 | RE10 | bidirectional | Master core function is port pin RE10; slave core alternate is S1RE10. |
| 58 | TDO/AN9/RP39/RB7 | bidirectional | Master core function is TDO/AN9/RP39/RB7 (JTAG data output TDO, ADC channel AN9, remappable RP39, port RB7); slave core alternates are S1MCLR1/S1AN6/S1RP39/S1PWM5H/S1RB7. |
| 59 | RE11 | bidirectional | Master core function is port pin RE11; slave core alternate is S1RE11. |
| 60 | PGD1/AN10/RP40/SCL1/RB8 | bidirectional | Master core function is PGD1/AN10/RP40/SCL1/RB8 (programming/debug data PGD1, ADC channel AN10, remappable RP40, I2C1 clock SCL1, port RB8); slave core alternates are S1PGD1/S1AN7/S1RP40/S1SCL1/S1RB8. |
| 61 | PGC1/AN11/RP41/SDA1/RB9 | input | Master core function is PGC1/AN11/RP41/SDA1/RB9 (programming/debug clock PGC1, ADC channel AN11, remappable RP41, I2C1 data SDA1, port RB9); slave core alternates are S1PGC1/S1RP41/S1SDA1/S1RB9. |
| 62 | ASCL2/RE12 | bidirectional | Master core function is alternate serial clock ASCL2 on port RE12; slave core alternate is S1RE12. |
| 63 | RP52/RC4 | bidirectional | Master core function is RP52/RC4 (remappable I/O RP52, port RC4); slave core alternates are S1RP52/S1PWM2H/S1RC4. |
| 64 | ASDA2/RE13 | bidirectional | Master core function is alternate serial data ASDA2 on port RE13; slave core alternate is S1RE13. |
| 65 | RP53/RC5 | bidirectional | Master core function is RP53/RC5 (remappable I/O RP53, port RC5); slave core alternates are S1RP53/S1PWM2L/S1RC5. |
| 66 | RP58/RC10 | bidirectional | Master core function is RP58/RC10 (remappable I/O RP58, port RC10); slave core alternates are S1RP58/S1PWM1H/S1RC10. |
| 67 | RP59/RC11 | bidirectional | Master core function is RP59/RC11 (remappable I/O RP59, port RC11); slave core alternates are S1RP59/S1PWM1L/S1RC11. |
| 68 | RP68/RD4 | bidirectional | Master core function is RP68/RD4 (remappable I/O RP68, port RD4); slave core alternates are S1RP68/S1PWM3H/S1RD4. |
| 69 | RP67/RD3 | bidirectional | Master core function is RP67/RD3 (remappable I/O RP67, port RD3); slave core alternates are S1RP67/S1PWM3L/S1RD3. |
| 70 | VSS | power_in | Digital ground pin. |
| 71 | VDD | power_in | Digital supply pin; the datasheet headline operating range is 3V to 3.6V. |
| 72 | RP66/RD2 | bidirectional | Master core function is RP66/RD2 (remappable I/O RP66, port RD2); slave core alternates are S1RP66/S1PWM8L/S1RD2. |
| 73 | RP65/RD1 | bidirectional | Master core function is RP65/RD1 (remappable I/O RP65, port RD1); slave core alternates are S1RP65/S1PWM4H/S1RD1. |
| 74 | RP64/RD0 | bidirectional | Master core function is RP64/RD0 (remappable I/O RP64, port RD0); slave core alternates are S1RP64/S1PWM4L/S1RD0. |
| 75 | TMS/RP42/PWM3H/RB10 | bidirectional | Master core function is TMS/RP42/PWM3H/RB10 (JTAG mode select TMS, remappable RP42, PWM3H output, port RB10); slave core alternates are S1RP42/S1RB10. |
| 76 | TCK/RP43/PWM3L/RB11 | bidirectional | Master core function is TCK/RP43/PWM3L/RB11 (JTAG clock TCK, remappable RP43, PWM3L output, port RB11); slave core alternates are S1RP43/S1RB11. |
| 77 | RE14 | bidirectional | Master core function is port pin RE14; slave core alternate is S1RE14. |
| 78 | TDI/RP44/PWM2H/RB12 | bidirectional | Master core function is TDI/RP44/PWM2H/RB12 (JTAG data input TDI, remappable RP44, PWM2H output, port RB12); slave core alternates are S1RP44/S1RB12. |
| 79 | RE15 | bidirectional | Master core function is port pin RE15; slave core alternate is S1RE15. |
| 80 | RP45/PWM2L/RB13 | bidirectional | Master core function is RP45/PWM2L/RB13 (remappable I/O RP45, PWM2L output, port RB13); slave core alternates are S1RP45/S1RB13. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-80(12x12) |
| Category | Embedded Processors & Controllers |
| Pins | 80 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating voltage (family headline, Operating Conditions bullet) | | 3 | | 3.6 | V | | 1 |
## CAD (KiCad official)
- Symbol: `DSPIC33CH512MP208-I`
- Footprint: `Package_QFP:TQFP-80_12x12mm_P0.5mm`
- 3D model: TQFP-80(12x12) (KiCad packages3D, STEP)
- 3D model files: `dspic33ch512mp208-i-etched.step` / `dspic33ch512mp208-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dspic33ch512mp208-i.step` / `dspic33ch512mp208-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/dspic33ch512mp208-i-datasheet.pdf) (16 pp, sha256 `856e174c082eba86`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dspic33ch512mp208-i-datasheet.pdf)