component

dsPIC33CH256MP506-I/MR

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Microchip Tech Pre-ordered MCUs, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersdspic33ch256mp506-ifactory-2.0.0extractor-text

Changed since verified dsPIC33CH256MP506-I

by Ray · last 30 Oct 2026 · 1 record · files changed since
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinschanged since
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: dsPIC33CH256MP506-I · QFN-64-EP(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 16-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-6ot49nhg/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! dspic33ch256mp506-i.kicad_sym✓ dspic33ch256mp506-i.kicad_mod✓ dspic33ch256mp506-i.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers dspic33ch256mp506-i: symbol viewer · Ray
dspic33ch256mp506-i-etched.glb Publish 0.1.0 · Ray
dspic33ch256mp506-i-etched.step dspic33ch256mp506-i: factory component page (tier=mfr) · Ray
dspic33ch256mp506-i-hero.glb dspic33ch256mp506-i: hero GLB from the etched model (keeps the MPN mark) · Ray
dspic33ch256mp506-i-hero.overlay.json Publish 0.1.0 · Ray
dspic33ch256mp506-i-mr-hero.glb Publish 0.1.1 · Ray
dspic33ch256mp506-i-mr-hero.overlay.json Publish 0.1.1 · Ray
dspic33ch256mp506-i.glb Publish 0.1.0 · Ray
dspic33ch256mp506-i.kicad_mod Publish 0.1.0 · Ray
dspic33ch256mp506-i.kicad_sym dspic33ch256mp506-i: symbol repaired (body fitted to the names) · Ray
dspic33ch256mp506-i.lbr dspic33ch256mp506-i-mr: renamed from dspic33ch256mp506-i, the part it was built from (dsPIC33CH256MP506-I/MR); family l… · Ray
dspic33ch256mp506-i.step Publish 0.1.0 · Ray
package.json Publish 0.1.1 · Ray
page.json Publish 0.1.1 · Ray
README.md dspic33ch256mp506-i-mr: renamed from dspic33ch256mp506-i, the part it was built from (dsPIC33CH256MP506-I/MR); family l… · Ray
verification.json Verified: Published by the parts factory: tier mfr, 65 pins · Ray

dsPIC33CH256MP506-I/MR

Microchip Tech · Pre-ordered MCUs · QFN-64-EP(9x9)

dsPIC33CH256MP506-I from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RP46/PWM1H/RB14 bidirectional Master core RB14 I/O with remappable pin RP46 and PWM1H; Slave core function S1RP46/S1RB14.
2 RP47/PWM1L/RB15 bidirectional Master core RB15 I/O with remappable pin RP47 and PWM1L; Slave core function S1RP47/S1RB15.
3 RP60/PWM4H/RC12 bidirectional Master core RC12 I/O with remappable pin RP60 and PWM4H; Slave core function S1RP60/S1RC12.
4 RP61/PWM4L/RC13 bidirectional Master core RC13 I/O with remappable pin RP61 and PWM4L; Slave core function S1RP61/S1RC13.
5 RP62/RC14 bidirectional Master core RC14 I/O with remappable pin RP62; Slave core function S1RP62/S1PWM7H/S1RC14.
6 RP63/RC15 bidirectional Master core RC15 I/O with remappable pin RP63; Slave core function S1RP63/S1PWM7L/S1RC15.
7 MCLR input Master clear (reset) input, shared by Master and Slave cores.
8 PCI22/RD15 bidirectional Master core RD15 I/O with PWM PCI22 input; Slave core function S1PCI22/S1RD15.
9 VSS power_in Ground reference for digital logic and I/O.
10 VDD power_in Positive supply for digital logic and I/O (device operates at 3V to 3.6V).
11 PCI21/RD14 bidirectional Master core RD14 I/O with PWM PCI21 input; Slave core function S1ANN1/S1PGA2N2/S1PCI21/S1RD14.
12 RD13 bidirectional Master core RD13 I/O; Slave core function S1ANN0/S1PGA1N2/S1RD13.
13 AN12/IBIAS3/RP48/RC0 bidirectional Master core analog input AN12, IBIAS3 current bias output, remappable RP48 and RC0 I/O; Slave core function S1AN10/S1RP48/S1RC0.
14 AN0/CMP1A/RA0 bidirectional Master core analog input AN0, comparator 1 input CMP1A and RA0 I/O; Slave core function S1RA0.
15 AN1/RA1 bidirectional Master core analog input AN1 and RA1 I/O; Slave core function S1AN15/S1RA1.
16 AN2/RA2 bidirectional Master core analog input AN2 and RA2 I/O; Slave core function S1AN16/S1RA2.
17 AN3/IBIAS0/RA3 bidirectional Master core analog input AN3, IBIAS0 current bias output and RA3 I/O; Slave core function S1AN0/S1CMP1A/S1PGA1P1/S1RA3.
18 AN4/IBIAS1/RA4 bidirectional Master core analog input AN4, IBIAS1 current bias output and RA4 I/O; Slave core function S1MCLR3/S1AN1/S1CMP2A/S1PGA2P1/S1PGA3P2/S1RA4.
19 AVDD power_in Positive supply for the analog modules.
20 AVSS power_in Ground reference for the analog modules.
21 RD12 bidirectional Master core RD12 I/O; Slave core function S1AN14/S1PGA2P2/S1RD12.
22 AN13/ISRC0/RP49/RC1 bidirectional Master core analog input AN13, ISRC0 current source output, remappable RP49 and RC1 I/O; Slave core function S1ANA1/S1RP49/S1RC1.
23 AN14/ISRC1/RP50/RC2 bidirectional Master core analog input AN14, ISRC1 current source output, remappable RP50 and RC2 I/O; Slave core function S1ANA0/S1RP50/S1RC2.
24 RP54/RC6 bidirectional Master core RC6 I/O with remappable pin RP54; Slave core function S1AN11/S1CMP1B/S1RP54/S1RC6.
25 VDD power_in Positive supply for digital logic and I/O (device operates at 3V to 3.6V).
26 VSS power_in Ground reference for digital logic and I/O.
27 CMP1B/RP51/RC3 bidirectional Master core comparator 1 input CMP1B, remappable RP51 and RC3 I/O; Slave core function S1AN8/S1CMP3B/S1RP51/S1RC3.
28 OSCI/CLKI/AN5/RP32/RB0 bidirectional Master core oscillator input OSCI/CLKI, analog input AN5, remappable RP32 and RB0 I/O; Slave core function S1AN5/S1RP32/S1RB0.
29 OSCO/CLKO/AN6/IBIAS2/RP33/RB1 bidirectional Master core oscillator output OSCO/CLKO, analog input AN6, IBIAS2 current bias output, remappable RP33 and RB1 I/O; Slave core function S1AN4/S1RP33/S1RB1.
30 RD11 bidirectional Master core RD11 I/O; Slave core function S1AN17/S1PGA1P2/S1RD11.
31 ISRC3/RD10 bidirectional Master core ISRC3 current source output and RD10 I/O; Slave core function S1AN13/S1CMP2B/S1RD10.
32 AN15/ISRC2/RP55/RC7 bidirectional Master core analog input AN15, ISRC2 current source output, remappable RP55 and RC7 I/O; Slave core function S1AN12/S1RP55/S1RC7.
33 DACOUT/AN7/CMP1D/RP34/INT0/RB2 bidirectional Master core DAC output DACOUT, analog input AN7, comparator input CMP1D, remappable RP34, INT0 and RB2 I/O; Slave core function S1MCLR2/S1AN3/S1ANC0/S1ANC1/S1CMP1D/S1CMP2D/S1CMP3D/S1RP34/S1INT0/S1RB2.
34 PGD2/AN8/RP35/RB3 bidirectional Master core programming/debug data PGD2, analog input AN8, remappable RP35 and RB3 I/O; Slave core function S1PGD2/S1AN18/S1CMP3A/S1PGA3P1/S1RP35/S1RB3.
35 PGC2/RP36/RB4 bidirectional Master core programming/debug clock PGC2, remappable RP36 and RB4 I/O; Slave core function S1PGC2/S1AN9/S1RP36/S1PWM5L/S1RB4.
36 RP56/ASDA1/SCK2/RC8 bidirectional Master core RC8 I/O with remappable RP56, alternate I2C data ASDA1 and SPI clock SCK2; Slave core function S1RP56/S1ASDA1/S1SCK1/S1RC8.
37 RP57/ASCL1/SDI2/RC9 bidirectional Master core RC9 I/O with remappable RP57, alternate I2C clock ASCL1 and SPI data input SDI2; Slave core function S1RP57/S1ASCL1/S1SDI1/S1RC9.
38 PCI20/RD9 bidirectional Master core RD9 I/O with PWM PCI20 input; Slave core function S1PCI20/S1RD9.
39 SDO2/PCI19/RD8 bidirectional Master core SPI data output SDO2, PWM PCI19 input and RD8 I/O; Slave core function S1SDO1/S1PCI19/S1RD8.
40 VSS power_in Ground reference for digital logic and I/O.
41 VDD power_in Positive supply for digital logic and I/O (device operates at 3V to 3.6V).
42 RP71/RD7 bidirectional Master core RD7 I/O with remappable pin RP71; Slave core function S1RP71/S1PWM8H/S1RD7.
43 RP70/RD6 bidirectional Master core RD6 I/O with remappable pin RP70; Slave core function S1RP70/S1PWM6H/S1RD6.
44 RP69/RD5 bidirectional Master core RD5 I/O with remappable pin RP69; Slave core function S1RP69/S1PWM6L/S1RD5.
45 PGD3/RP37/SDA2/RB5 bidirectional Master core programming/debug data PGD3, remappable RP37, I2C data SDA2 and RB5 I/O; Slave core function S1PGD3/S1RP37/S1RB5.
46 PGC3/RP38/SCL2/RB6 bidirectional Master core programming/debug clock PGC3, remappable RP38, I2C clock SCL2 and RB6 I/O; Slave core function S1PGC3/S1RP38/S1RB6.
47 TDO/AN9/RP39/RB7 bidirectional Master core JTAG data output TDO, analog input AN9, remappable RP39 and RB7 I/O; Slave core function S1MCLR1/S1AN6/S1RP39/S1PWM5H/S1RB7.
48 PGD1/AN10/RP40/SCL1/RB8 bidirectional Master core programming/debug data PGD1, analog input AN10, remappable RP40, I2C clock SCL1 and RB8 I/O; Slave core function S1PGD1/S1AN7/S1RP40/S1SCL1/S1RB8.
49 PGC1/AN11/RP41/SDA1/RB9 bidirectional Master core programming/debug clock PGC1, analog input AN11, remappable RP41, I2C data SDA1 and RB9 I/O; Slave core function S1PGC1/S1RP41/S1SDA1/S1RB9.
50 RP52/RC4 bidirectional Master core RC4 I/O with remappable pin RP52; Slave core function S1RP52/S1PWM2H/S1RC4.
51 RP53/RC5 bidirectional Master core RC5 I/O with remappable pin RP53; Slave core function S1RP53/S1PWM2L/S1RC5.
52 RP58/RC10 bidirectional Master core RC10 I/O with remappable pin RP58; Slave core function S1RP58/S1PWM1H/S1RC10.
53 RP59/RC11 bidirectional Master core RC11 I/O with remappable pin RP59; Slave core function S1RP59/S1PWM1L/S1RC11.
54 RP68/RD4 bidirectional Master core RD4 I/O with remappable pin RP68; Slave core function S1RP68/S1PWM3H/S1RD4.
55 RP67/RD3 bidirectional Master core RD3 I/O with remappable pin RP67; Slave core function S1RP67/S1PWM3L/S1RD3.
56 VSS power_in Ground reference for digital logic and I/O.
57 VDD power_in Positive supply for digital logic and I/O (device operates at 3V to 3.6V).
58 RP66/RD2 bidirectional Master core RD2 I/O with remappable pin RP66; Slave core function S1RP66/S1PWM8L/S1RD2.
59 RP65/RD1 bidirectional Master core RD1 I/O with remappable pin RP65; Slave core function S1RP65/S1PWM4H/S1RD1.
60 RP64/RD0 bidirectional Master core RD0 I/O with remappable pin RP64; Slave core function S1RP64/S1PWM4L/S1RD0.
61 TMS/RP42/PWM3H/RB10 bidirectional Master core JTAG mode select TMS, remappable RP42, PWM3H and RB10 I/O; Slave core function S1RP42/S1RB10.
62 TCK/RP43/PWM3L/RB11 bidirectional Master core JTAG clock TCK, remappable RP43, PWM3L and RB11 I/O; Slave core function S1RP43/S1RB11.
63 TDI/RP44/PWM2H/RB12 bidirectional Master core JTAG data input TDI, remappable RP44, PWM2H and RB12 I/O; Slave core function S1RP44/S1RB12.
64 RP45/PWM2L/RB13 bidirectional Master core RB13 I/O with remappable pin RP45 and PWM2L; Slave core function S1RP45/S1RB13.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(9x9)
Category Embedded Processors & Controllers
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating supply voltage range VDD 3 3.6 V 3V to 3.6V, -40°C to +125°C 1
Operating temperature range -40 125 °C 3V to 3.6V 1
Master core operating frequency 200 MHz Master: Up to 100 MIPS @ 200 MHz 1
Slave core operating frequency 240 MHz Slave: Up to 120 MIPS @ 240 MHz 1

CAD (KiCad official)

  • Symbol: dsPIC33CH256MP506-I
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: dspic33ch256mp506-i-etched.step / dspic33ch256mp506-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dspic33ch256mp506-i.step / dspic33ch256mp506-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (16 pp, sha256 6d82f62238e7b1d8, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Other parts in this family

This page is dsPIC33CH256MP506-I/MR. These part numbers share its family name but are different parts (another package, rating or grade), each with its own page:

  • dsPIC33CH256MP506-I/PT