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DS92LV2421SQ

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Texas Instruments Serializers / Deserializers, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS92LV2421SQ

Texas Instruments · Serializers / Deserializers · WQFN-48-EP(7x7)

DS92LV2421SQ from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DI22 input Parallel interface data input (blue channel bus DI[23:16]), LVCMOS with pulldown.
2 DI23 input Parallel interface data input, MSB of the 8-bit blue channel (DI23 = B7), LVCMOS with pulldown.
3 CI2 input Control signal input for horizontal sync; pulse width must be 3 clocks or longer when the control signal filter is enabled, and the signal is limited to 2 transitions per 130 clocks.
4 CI3 input Control signal input for vertical sync, limited to 1 transition per 130 clock cycles so the minimum pulse width is 130 clock cycles.
5 CI1 input Control signal input for data enable; pulse width must be 3 clocks or longer when the control signal filter is enabled, and the signal is limited to 2 transitions per 130 clocks.
6 ID[x] input I2C serial control bus device ID address select (optional, analog), set by a resistor to ground and a 10-kΩ pullup to the 1.8-V rail.
7 VDDL power_in Logic power supply, 1.8 V ± 5%.
8 SCL input I2C serial control bus clock input (optional), LVCMOS; requires an external pullup resistor to VDDIO.
9 SDA bidirectional I2C serial control bus data input or output (optional), LVCMOS open drain; requires an external pullup resistor to VDDIO.
10 CLKIN input Pixel clock input, LVCMOS with pulldown; latch or data strobe edge is set by RFB.
11 RFB input Clock input latch or data strobe edge select, LVCMOS with pulldown; RFB = 1 latches on the rising edge and RFB = 0 on the falling edge.
12 CONFIG[0] input Configuration input (LSB of CONFIG[1:0]), LVCMOS with pulldown; 00 disables and 01 enables the control signal filter.
13 CONFIG[1] input Configuration input (MSB of CONFIG[1:0]), LVCMOS with pulldown; 10 selects DS90UR124/DS99R124Q-Q1 reverse compatibility and 11 selects DS90C124 reverse compatibility.
14 VDDP power_in PLL power supply, 1.8 V ± 5%.
15 RES0 input Reserved pin, must be tied low, LVCMOS with pulldown.
16 RES1 input Reserved pin, must be tied low, LVCMOS with pulldown.
17 VDDHS power_in TX high-speed logic power supply, 1.8 V ± 5%.
18 RES2 input Reserved pin, must be tied low, LVCMOS with pulldown.
19 DOUT- output Inverting CML serial output, which must be AC-coupled with a 0.1-µF capacitor.
20 DOUT+ output Non-inverting CML serial output, which must be AC-coupled with a 0.1-µF capacitor.
21 PDB input Power-down input, LVCMOS with pulldown; PDB = 1 enables the serializer, and PDB = 0 powers it down with DOUT± both logic high.
22 VDDTX power_in Output driver power supply, 1.8 V ± 5%.
23 De-Emph input De-emphasis control, analog with pullup; leaving the pin floating disables de-emphasis, and a resistor to GND enables it.
24 VODSEL input Differential driver output voltage select, LVCMOS with pulldown; VODSEL = 1 gives VOD ±420 mV (840 mVp-p typical), and VODSEL = 0 gives ±280 mV (560 mVp-p typical).
25 DI0 input Parallel interface data input, LVCMOS with pulldown; DI0 is the LSB of the red channel.
26 DI1 input Parallel interface data input, LVCMOS with pulldown, part of the red channel bus DI[7:0].
27 DI2 input Parallel interface data input, LVCMOS with pulldown, part of the red channel bus DI[7:0].
28 DI3 input Parallel interface data input, LVCMOS with pulldown, part of the red channel bus DI[7:0].
29 DI4 input Parallel interface data input, LVCMOS with pulldown, part of the red channel bus DI[7:0].
30 VDDIO power_in LVCMOS I/O power supply, 1.8 V ± 5% or 3.3 V ± 10%.
31 BISTEN input BIST mode enable input (optional), LVCMOS with pulldown; 0 disables BIST and 1 enables it.
32 DI5 input Parallel interface data input, LVCMOS with pulldown, part of the red channel bus DI[7:0].
33 DI6 input Parallel interface data input, LVCMOS with pulldown, part of the red channel bus DI[7:0].
34 DI7 input Parallel interface data input, MSB of the 8-bit red channel (DI7 = R7), LVCMOS with pulldown.
35 DI8 input Parallel interface data input, LSB of the 8-bit green channel (DI8 = G0), LVCMOS with pulldown.
36 DI9 input Parallel interface data input, LVCMOS with pulldown, part of the green channel bus DI[15:8].
37 DI10 input Parallel interface data input, LVCMOS with pulldown, part of the green channel bus DI[15:8].
38 DI11 input Parallel interface data input, LVCMOS with pulldown, part of the green channel bus DI[15:8].
39 DI12 input Parallel interface data input, LVCMOS with pulldown, part of the green channel bus DI[15:8].
40 DI13 input Parallel interface data input, LVCMOS with pulldown, part of the green channel bus DI[15:8].
41 DI14 input Parallel interface data input, LVCMOS with pulldown, part of the green channel bus DI[15:8].
42 DI15 input Parallel interface data input, MSB of the 8-bit green channel (DI15 = G7), LVCMOS with pulldown.
43 DI16 input Parallel interface data input, LSB of the 8-bit blue channel (DI16 = B0), LVCMOS with pulldown.
44 DI17 input Parallel interface data input, LVCMOS with pulldown, part of the blue channel bus DI[23:16].
45 DI18 input Parallel interface data input, LVCMOS with pulldown, part of the blue channel bus DI[23:16].
46 DI19 input Parallel interface data input, LVCMOS with pulldown, part of the blue channel bus DI[23:16].
47 DI20 input Parallel interface data input, LVCMOS with pulldown, part of the blue channel bus DI[23:16].
48 DI21 input Parallel interface data input, LVCMOS with pulldown, part of the blue channel bus DI[23:16].
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48-EP(7x7)
Category Communication Interface Chip/UART/485/232
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDn (1.8 V) VDDn -0.3 2.5 V 10
Supply voltage VDDIO VDDIO -0.3 4 V 10
LVCMOS I/O voltage -0.3 V 10
Receiver input voltage -0.3 V 10
Driver output voltage -0.3 V 10
Maximum power dissipation capacity at 25°C (48L RHS package) 225 mW 48L RHS package 10
Junction temperature TJ 150 °C 10
Storage temperature Tstg -65 150 °C 10
VDDn supply voltage VDDn 1.71 1.8 1.89 V 10
VDDIO LVCMOS supply voltage (1.8 V option) VDDIO 1.71 1.8 1.89 V 10
VDDIO LVCMOS supply voltage (3.3 V option) VDDIO 3 3.3 3.6 V 10
Clock frequency 10 75 MHz 10
Supply noise 50 mVp-p 10
Operating free-air temperature TA -40 25 85 °C 10
Junction-to-ambient thermal resistance (RHS 48 pins) RθJA 30.3 °C/W Based on nine thermal vias 11
Junction-to-case (top) thermal resistance (RHS 48 pins) RθJC(top) 11.5 °C/W Based on nine thermal vias 11
Junction-to-board thermal resistance (RHS 48 pins) RθJB 7.3 °C/W 11
Junction-to-case (bottom) thermal resistance (RHS 48 pins) RθJC(bot) 2.7 °C/W 11
High level input voltage VIH 2.2 V VDDIO = 3 V to 3.6 V 11
Low level input voltage VIL 0.8 V VDDIO = 3 V to 3.6 V 11
Input current IIN -15 1 15 µA VIN = 0 V or VDDIO, VDDIO = 3 V to 3.6 V 11
Differential output voltage (VODSEL = 0) VOD 205 280 355 mV RL = 100 Ω, de-emphasis = disabled, VODSEL = 0 11
Differential output voltage (VODSEL = 1) VOD 320 420 520 mV RL = 100 Ω, de-emphasis = disabled, VODSEL = 1 11
Differential output voltage p-p (VODSEL = 0) VOD 560 mVp-p (DOUT+), (DOUT-), RL = 100 Ω, de-emphasis = disabled, VODSEL = 0 11
Differential output voltage p-p (VODSEL = 1) VOD 840 mVp-p (DOUT+), (DOUT-), RL = 100 Ω, de-emphasis = disabled, VODSEL = 1 11
Output voltage unbalance ΔVOD 1 50 mV RL = 100 Ω, de-emphasis = disabled, VODSEL = L 11
Offset voltage (single-ended, VODSEL = 0) VOS 1.65 V At TP A and B, RL = 100 Ω, de-emphasis = disabled, VODSEL = 0 11
Offset voltage (single-ended, VODSEL = 1) VOS 1.575 V At TP A and B, RL = 100 Ω, de-emphasis = disabled, VODSEL = 1 11
Offset voltage unbalance (single-ended) ΔVOS 1 mV At TP A and B, RL = 100 Ω, de-emphasis = disabled 11
Output short circuit current IOS -36 mA DOUT± = 0 V, de-emphasis = disabled, VODSEL = 0 11
Internal output termination resistor RTO 80 100 120 Ω DOUT+ and DOUT- pins 11
Serializer supply current (includes load current), VDD IDDT1 75 90 mA RL = 100 Ω, CLKIN = 75 MHz, checker board, de-emphasis = 3 kΩ, VODSEL = H, VDD = 1.89 V 12
Serializer supply current (includes load current), VDDIO = 1.89 V IDDIOT1 3 5 mA RL = 100 Ω, CLKIN = 75 MHz, checker board, de-emphasis = 3 kΩ, VODSEL = H, VDDIO = 1.89 V 12
Serializer supply current (includes load current), VDDIO = 3.6 V IDDIOT1 11 15 mA RL = 100 Ω, CLKIN = 75 MHz, checker board, de-emphasis = 3 kΩ, VODSEL = H, VDDIO = 3.6 V 12
Serializer supply current (includes load current), VDD IDDT2 65 80 mA RL = 100 Ω, CLKIN = 75 MHz, checker board, de-emphasis = 6 kΩ, VODSEL = L, VDD = 1.89 V 12
Serializer supply current power-down, VDD IDDZ 40 1000 µA PDB = 0 V, all other LVCMOS inputs = 0 V, VDD = 1.89 V 12
Serializer supply current power-down, VDDIO = 1.89 V IDDIOZ 5 10 µA PDB = 0 V, all other LVCMOS inputs = 0 V, VDDIO = 1.89 V 12
Serializer supply current power-down, VDDIO = 3.6 V IDDIOZ 10 20 µA PDB = 0 V, all other LVCMOS inputs = 0 V, VDDIO = 3.6 V 12
Input high level voltage SDA and SCL VIH 2.2 V 13
Input low level voltage SDA and SCL VIL 0.8 V 13
Output low level voltage SDA VOL 0.4 V SDA, IOL = 1.25 mA, VDDIO = 3.3 V 13
Input current SDA or SCL Iin -15 15 µA SDA or SCL, Vin = VDDIO or GND 13
Input capacitance SDA or SCL Cin 5 pF SDA or SCL 13
Transmit input CLKIN period tTCP 13.3 100 ns 10 MHz to 75 MHz 13
CLKIN input transition time tCLKT 0.5 2.4 ns 10 MHz to 75 MHz 13
Spread spectrum deviation frequency fdev -2 2 % spread spectrum at 75 MHz 13
Spread spectrum modulation frequency fmod 35 kHz spread spectrum at 75 MHz 13
Serializer output low-to-high transition time (VODSEL = 0) tLHT 200 ps RL = 100 Ω, de-emphasis = disabled, VODSEL = 0 14
Serializer output low-to-high transition time (VODSEL = 1) tLHT 200 ps RL = 100 Ω, de-emphasis = disabled, VODSEL = 1 14
Serializer output high-to-low transition time (VODSEL = 0) tHLT 200 ps RL = 100 Ω, de-emphasis = disabled, VODSEL = 0 14
Serializer output high-to-low transition time (VODSEL = 1) tHLT 200 ps RL = 100 Ω, de-emphasis = disabled, VODSEL = 1 14
Input data setup time to CLKIN tDIS 2 ns 14
Input data hold time from CLKIN tDIH 2 ns 14
Serializer output active to OFF delay tXZD 8 15 ns 14
Serializer PLL lock time tPLD 1.4 10 ms RL = 100 Ω 14

CAD (KiCad official)

  • Symbol: DS92LV2421SQ
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds92lv2421sq-etched.step / ds92lv2421sq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds92lv2421sq.step / ds92lv2421sq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (63 pp, sha256 fc1db9e30fd022db, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF