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DS92LV2411SQ

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Texas Instruments Serializers, Deserializers, WQFN-48-EP(7x7). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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DS92LV2411SQ

Texas Instruments · Serializers, Deserializers · WQFN-48-EP(7x7)

DS92LV2411SQ from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DI22 input Parallel LVCMOS data input with pull-down; blue channel bit B6 for 8-bit BLUE display.
2 DI23 input Parallel LVCMOS data input with pull-down; blue channel MSB (B7) for 8-bit BLUE display.
3 CI2 input LVCMOS control input with pull-down; Horizontal Sync input in display applications, with pulse width of 3 clocks or longer required when the control signal filter is enabled (CONFIG[1:0] = 01).
4 CI3 input LVCMOS control input with pull-down; Vertical Sync input in display applications, limited to 1 transition per 130 clock cycles.
5 CI1 input LVCMOS control input with pull-down; Data Enable input in display applications, with pulse width of 3 clocks or longer required when the control signal filter is enabled, and limited to 2 transitions per 130 clocks.
6 ID[x] passive Analog I2C device ID address select (optional), set by a resistor to ground and a 10 kΩ pull-up to the 1.8 V rail per Table 11.
7 VDDL power_in Logic power supply, 1.8 V ±5%.
8 SCL input Optional I2C serial control bus clock input, open drain, requires an external pull-up resistor to 3.3 V.
9 SDA bidirectional Optional I2C serial control bus data input/output, open drain, requires an external pull-up resistor to 3.3 V.
10 CLKIN input LVCMOS clock input with pull-down whose latch/data strobe edge is set by the RFB pin.
11 RFB input LVCMOS latch/data strobe edge select with pull-down: 1 latches data and control on the rising clock edge, 0 on the falling edge; also controllable via I2C.
12 CONFIG[0] input LVCMOS configuration input with pull-down (bit 0 of CONFIG[1:0]) selecting control signal filter enable or reverse-compatibility mode.
13 CONFIG[1] input LVCMOS configuration input with pull-down (bit 1 of CONFIG[1:0]) selecting control signal filter enable or reverse-compatibility mode.
14 VDDP power_in PLL power supply, 1.8 V ±5%.
15 RES2 input Reserved pin with pull-down; must be tied LOW.
16 RES1 input Reserved pin with pull-down; must be tied LOW.
17 VDDHS power_in TX high-speed logic power supply, 1.8 V ±5%.
18 RES0 input Reserved pin with pull-down; must be tied LOW.
19 DOUT- output Inverting CML serial output; must be AC coupled with a 0.1 µF capacitor.
20 DOUT+ output Non-inverting CML serial output; must be AC coupled with a 0.1 µF capacitor.
21 PDB input Power-down input with pull-down: 1 enables the serializer; 0 powers it down, driving DOUT± logic high, shutting down the PLL and resetting control registers.
22 VDDTX power_in Output driver power supply, 1.8 V ±5%.
23 De-Emph passive Analog de-emphasis control: leave open (float) to disable, or tie a resistor to GND to enable; can also be controlled via I2C register.
24 VODSEL input Differential driver output voltage select with pull-down: 1 gives CML VOD of ±420 mV (840 mVp-p typ) for long cable/de-emphasis, 0 gives ±280 mV (560 mVp-p typ) for short cable and low power.
25 DI0 input Parallel LVCMOS data input with pull-down; red channel LSB (R0) for 8-bit RED display.
26 DI1 input Parallel LVCMOS data input with pull-down; red channel bit R1 for 8-bit RED display.
27 DI2 input Parallel LVCMOS data input with pull-down; red channel bit R2 for 8-bit RED display.
28 DI3 input Parallel LVCMOS data input with pull-down; red channel bit R3 for 8-bit RED display.
29 DI4 input Parallel LVCMOS data input with pull-down; red channel bit R4 for 8-bit RED display.
30 VDDIO power_in LVCMOS I/O power supply, 1.8 V ±5% or 3.3 V ±10%.
31 BISTEN input BIST mode enable input with pull-down: 0 disables BIST (normal operation), 1 enables BIST.
32 DI5 input Parallel LVCMOS data input with pull-down; red channel bit R5 for 8-bit RED display.
33 DI6 input Parallel LVCMOS data input with pull-down; red channel bit R6 for 8-bit RED display.
34 DI7 input Parallel LVCMOS data input with pull-down; red channel MSB (R7) for 8-bit RED display.
35 DI8 input Parallel LVCMOS data input with pull-down; green channel LSB (G0) for 8-bit GREEN display.
36 DI9 input Parallel LVCMOS data input with pull-down; green channel bit G1 for 8-bit GREEN display.
37 DI10 input Parallel LVCMOS data input with pull-down; green channel bit G2 for 8-bit GREEN display.
38 DI11 input Parallel LVCMOS data input with pull-down; green channel bit G3 for 8-bit GREEN display.
39 DI12 input Parallel LVCMOS data input with pull-down; green channel bit G4 for 8-bit GREEN display.
40 DI13 input Parallel LVCMOS data input with pull-down; green channel bit G5 for 8-bit GREEN display.
41 DI14 input Parallel LVCMOS data input with pull-down; green channel bit G6 for 8-bit GREEN display.
42 DI15 input Parallel LVCMOS data input with pull-down; green channel MSB (G7) for 8-bit GREEN display.
43 DI16 input Parallel LVCMOS data input with pull-down; blue channel LSB (B0) for 8-bit BLUE display.
44 DI17 input Parallel LVCMOS data input with pull-down; blue channel bit B1 for 8-bit BLUE display.
45 DI18 input Parallel LVCMOS data input with pull-down; blue channel bit B2 for 8-bit BLUE display.
46 DI19 input Parallel LVCMOS data input with pull-down; blue channel bit B3 for 8-bit BLUE display.
47 DI20 input Parallel LVCMOS data input with pull-down; blue channel bit B4 for 8-bit BLUE display.
48 DI21 input Parallel LVCMOS data input with pull-down; blue channel bit B5 for 8-bit BLUE display.
DAP GND power_in Ground: large exposed metal pad at the bottom center of the WQFN package; connect to the ground plane with at least 9 vias.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48-EP(7x7)
Category Interface
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage, VDDn (1.8 V) -0.3 2.5 V 10
Supply Voltage, VDDIO -0.3 4 V 10
Junction Temperature 150 °C 10
Storage Temperature Range Tstg -65 150 °C 10
Supply Voltage (VDDn) 1.71 1.8 1.89 V 10
LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V 1.8 V option (OR 3.3 V option) 10
LVCMOS Supply Voltage (VDDIO) 3 3.3 3.6 V 3.3 V option (OR 1.8 V option) 10
Operating Free Air Temperature TA -40 25 85 °C 10
Clock Frequency 5 50 MHz 10
Supply Noise 50 mVP-P 10
Maximum dissipation capacity (RHS package footnote) 215 mW 48-pin RHS package 11
High Level Input Voltage VIH 2.2 V VDDIO = 3.0 to 3.6V 11
Low Level Input Voltage VIL 0.8 V VDDIO = 3.0 to 3.6V 11
Input Current IIN -15 1 15 μA VIN = 0V or VDDIO, VDDIO = 3.0 to 3.6V 11
Differential Output Voltage VOD 205 280 355 mV RL = 100Ω, De-emph = disabled, VODSEL = 0 11
Differential Output Voltage VOD 320 420 520 mV RL = 100Ω, De-emph = disabled, VODSEL = 1 11
Output Voltage Unbalance ΔVOD 1 50 mV RL = 100Ω, De-emph = disabled, VODSEL = L 11
Internal Output Termination Resistor RTO 80 100 120 Ω 11
Serializer Supply Current (checker board, includes load current) IDDT1 75 85 mA VDD = 1.89V, checker board pattern, RL = 100 Ω, De-emph = 3kΩ, VODSEL = H, CLKIN = 50 MHz 12
Serializer VDDIO Supply Current (checker board) IDDIOT1 3 5 mA VDDIO = 1.89V, checker board pattern, RL = 100 Ω, De-emph = 3kΩ, VODSEL = H, CLKIN = 50 MHz 12
Serializer VDDIO Supply Current (checker board) IDDIOT1 11 15 mA VDDIO = 3.6V, checker board pattern, RL = 100 Ω, De-emph = 3kΩ, VODSEL = H, CLKIN = 50 MHz 12
Serializer Supply Current (checker board, includes load current) IDDT2 65 75 mA VDD = 1.89V, checker board pattern, De-emph = 6kΩ, VODSEL = L 12
Serializer Supply Current Power-down IDDZ 40 1000 μA VDD = 1.89V, PDB = 0V, all other LVCMOS inputs = 0V 12
Serializer VDDIO Supply Current Power-down IDDIOZ 5 10 μA VDDIO = 1.89V, PDB = 0V, all other LVCMOS inputs = 0V 12
Serializer VDDIO Supply Current Power-down IDDIOZ 10 20 μA VDDIO = 3.6V, PDB = 0V, all other LVCMOS inputs = 0V 12
Input High Level Voltage (SDA and SCL) VIH 2.2 V 13
Input Low Level Voltage (SDA and SCL) VIL 0.8 V 13
Input Hysteresis VHY 50 mV printed as >50 mV 13
Output Low Voltage (SDA) VOL 0 0.4 V IOL = 1.25mA, VDDIO = 3.3V 13
Input Current (SDA or SCL) Iin -15 15 μA SDA or SCL, Vin = VDDIO or GND 13
Input Capacitance (SDA or SCL) Cin 5 pF SDA or SCL 13
CLKIN Input Period (transmit) tTCP 200 ns 5 MHz to 50 MHz 18
CLKIN Spread Spectrum Deviation fdev -0.02 0.02 kHz CLKIN at 50 MHz 18
Thermal resistance, junction-to-ambient RθJA 27.1 °C/W 48-pin RHS package 11
Thermal resistance, junction-to-case (top) RθJC(top) 4.5 °C/W 48-pin RHS package 11

CAD (KiCad official)

  • Symbol: DS92LV2411SQ
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds92lv2411sq-etched.step / ds92lv2411sq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds92lv2411sq.step / ds92lv2411sq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (58 pp, sha256 835ff796edbb01a3, retrieved 2026-10-21, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF