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DS92LV090ATVEH

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Texas Instruments LVDS ICs, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS92LV090ATVEH

Texas Instruments · LVDS ICs · TQFP-64(10x10)

DS92LV090ATVEH from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect; leave unconnected.
2 DIN input TTL Driver Input; encodes to Bus LVDS differential output with VIH ≥ 2.0V, VIL ≤ 0.8V.
3 RO output TTL Receiver Output; decodes Bus LVDS differential input with 3.2ns maximum propagation delay.
4 GND power_in Power ground for digital circuitry; internally connected pins for low impedance.
5 GND power_in Power ground for digital circuitry; internally connected pins for low impedance.
6 DIN input TTL Driver Input; encodes to Bus LVDS differential output with VIH ≥ 2.0V, VIL ≤ 0.8V.
7 RO output TTL Receiver Output; decodes Bus LVDS differential input with 3.2ns maximum propagation delay.
8 NC unconnected No connect; leave unconnected.
9 GND power_in Power ground for digital circuitry; internally connected pins for low impedance.
10 VCC power_in Positive power supply for digital circuitry; operating range 3.0V to 3.6V.
11 NC unconnected No connect; leave unconnected.
12 DIN input TTL Driver Input; encodes to Bus LVDS differential output with VIH ≥ 2.0V, VIL ≤ 0.8V.
13 RO output TTL Receiver Output; decodes Bus LVDS differential input with 3.2ns maximum propagation delay.
14 GND power_in Power ground for digital circuitry; internally connected pins for low impedance.
15 VCC power_in Positive power supply for digital circuitry; operating range 3.0V to 3.6V.
16 DE input Driver Enable TTL Input (active high); enables driver outputs when high with VIH ≥ 2.0V, VIL ≤ 0.8V.
17 RE input Receiver Enable TTL Input (active low); enables receiver outputs when low with VIH ≥ 2.0V, VIL ≤ 0.8V.
18 DIN input TTL Driver Input; encodes to Bus LVDS differential output with VIH ≥ 2.0V, VIL ≤ 0.8V.
19 RO output TTL Receiver Output; decodes Bus LVDS differential input with 3.2ns maximum propagation delay.
20 DIN input TTL Driver Input; encodes to Bus LVDS differential output with VIH ≥ 2.0V, VIL ≤ 0.8V.
21 RO output TTL Receiver Output; decodes Bus LVDS differential input with 3.2ns maximum propagation delay.
22 DIN input TTL Driver Input; encodes to Bus LVDS differential output with VIH ≥ 2.0V, VIL ≤ 0.8V.
23 RO output TTL Receiver Output; decodes Bus LVDS differential input with 3.2ns maximum propagation delay.
24 VCC power_in Positive power supply for digital circuitry; operating range 3.0V to 3.6V.
25 GND power_in Power ground for digital circuitry; internally connected pins for low impedance.
26 DO−/RI− bidirectional Complementary Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
27 DO+/RI+ bidirectional True Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
28 AGND power_in Power ground for analog circuitry; internally connected pins for low impedance.
29 AVCC power_in Positive power supply for analog circuitry; operating range 3.0V to 3.6V, internally connected.
30 DO−/RI− bidirectional Complementary Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
31 DO+/RI+ bidirectional True Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
32 AVCC power_in Positive power supply for analog circuitry; operating range 3.0V to 3.6V, internally connected.
33 AGND power_in Power ground for analog circuitry; internally connected pins for low impedance.
34 DO−/RI− bidirectional Complementary Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
35 DO+/RI+ bidirectional True Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
36 DO−/RI− bidirectional Complementary Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
37 DO+/RI+ bidirectional True Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
38 NC unconnected No connect; leave unconnected.
39 NC unconnected No connect; leave unconnected.
40 DO−/RI− bidirectional Complementary Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
41 DO+/RI+ bidirectional True Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
42 AVCC power_in Positive power supply for analog circuitry; operating range 3.0V to 3.6V, internally connected.
43 AGND power_in Power ground for analog circuitry; internally connected pins for low impedance.
44 DO−/RI− bidirectional Complementary Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
45 DO+/RI+ bidirectional True Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
46 DO−/RI− bidirectional Complementary Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
47 DO+/RI+ bidirectional True Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
48 AVCC power_in Positive power supply for analog circuitry; operating range 3.0V to 3.6V, internally connected.
49 AGND power_in Power ground for analog circuitry; internally connected pins for low impedance.
50 DO−/RI− bidirectional Complementary Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
51 DO+/RI+ bidirectional True Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
52 AVCC power_in Positive power supply for analog circuitry; operating range 3.0V to 3.6V, internally connected.
53 AGND power_in Power ground for analog circuitry; internally connected pins for low impedance.
54 DO−/RI− bidirectional Complementary Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
55 DO+/RI+ bidirectional True Bus LVDS driver output and receiver input; 300mV typical differential voltage with ±100mV receiver sensitivity over 0.1V to 2.3V common mode range.
56 GND power_in Power ground for digital circuitry; internally connected pins for low impedance.
57 VCC power_in Positive power supply for digital circuitry; operating range 3.0V to 3.6V.
58 DIN input TTL Driver Input; encodes to Bus LVDS differential output with VIH ≥ 2.0V, VIL ≤ 0.8V.
59 RO output TTL Receiver Output; decodes Bus LVDS differential input with 3.2ns maximum propagation delay.
60 DIN input TTL Driver Input; encodes to Bus LVDS differential output with VIH ≥ 2.0V, VIL ≤ 0.8V.
61 RO output TTL Receiver Output; decodes Bus LVDS differential input with 3.2ns maximum propagation delay.
62 DIN input TTL Driver Input; encodes to Bus LVDS differential output with VIH ≥ 2.0V, VIL ≤ 0.8V.
63 RO output TTL Receiver Output; decodes Bus LVDS differential input with 3.2ns maximum propagation delay.
64 VCC power_in Positive power supply for digital circuitry; operating range 3.0V to 3.6V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Interface
Pins 64

CAD (KiCad official)

  • Symbol: DS92LV090ATVEH
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ds92lv090atveh-etched.step / ds92lv090atveh-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds92lv090atveh.step / ds92lv090atveh.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 25fcdfa15fe7c233, retrieved 2026-10-06, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF