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DS91M124TMAX

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Texas Instruments LVDS ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS91M124TMAX

Texas Instruments · LVDS ICs · SOIC-16

DS91M124TMAX from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DE0 input LVCMOS driver enable for channel 0: low disables the driver output, high enables it, with a 300 kΩ internal pulldown.
2 DE1 input LVCMOS driver enable for channel 1: low disables the driver output, high enables it, with a 300 kΩ internal pulldown.
3 DE2 input LVCMOS driver enable for channel 2: low disables the driver output, high enables it, with a 300 kΩ internal pulldown.
4 VDD power_in Power supply pin, +3.3V ± 0.3V.
5 GND power_in Power ground pin.
6 DI input LVCMOS driver input pin shared by all four M-LVDS drivers.
7 N/C unconnected No connect pin.
8 DE3 input LVCMOS driver enable for channel 3: low disables the driver output, high enables it, with a 300 kΩ internal pulldown.
9 B3 tri_state Inverting M-LVDS driver output for channel 3.
10 A3 tri_state Non-inverting M-LVDS driver output for channel 3.
11 A2 tri_state Non-inverting M-LVDS driver output for channel 2.
12 B2 tri_state Inverting M-LVDS driver output for channel 2.
13 B1 tri_state Inverting M-LVDS driver output for channel 1.
14 A1 tri_state Non-inverting M-LVDS driver output for channel 1.
15 A0 tri_state Non-inverting M-LVDS driver output for channel 0.
16 B0 tri_state Inverting M-LVDS driver output for channel 0.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Interface
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power Supply Voltage -0.3 4 V 3
LVCMOS Input Voltage -0.3 V Max printed as (VDD + 0.3V) 3
M-LVDS Output Voltage -1.9 5.5 V 3
Junction Temperature 140 °C 3
Storage Temperature Range -65 150 °C 3
Lead Temperature Range Soldering 260 °C 4 sec. 3
Maximum Package Power Dissipation 2.21 W D0016A package, @ +25°C 3
ESD Susceptibility HBM 8 kV Human Body Model, JESD22-A114C 3
ESD Susceptibility MM 250 V Machine Model, JESD22-A115-A 3
ESD Susceptibility CDM 1250 V Field Induced Charge Device Model, JESD22-C101-C 3
Supply Voltage VDD 3 3.3 3.6 V 3
Voltage at Any Bus Terminal (Separate or Common-Mode) -1.4 3.8 V 3
LVTTL Input Voltage High VIH 2 V Max printed as VDD 3
LVTTL Input Voltage Low VIL 0 0.8 V 3
Operating Free Air Temperature TA -40 25 85 °C 3
High-Level Input Voltage VIH 2 V LVCMOS; max printed as VDD 4
Low-Level Input Voltage VIL 0.8 V LVCMOS; min printed as GND 4
High-Level Input Current IIH -15 1 15 μA VIH = 3.6V 4
Low-Level Input Current IIL -15 1 15 μA VIL = 0V 4
Input Clamp Voltage VCL -1.5 V IIN = -18 mA 4
Differential Output Voltage Magnitude /VAB/ 480 650 mV RL = 50Ω, CL = 5 pF, Figure 2 4
Change in Differential Output Voltage Magnitude Between Logic States ΔVAB -50 50 mV Figure 4 4
Steady-State Common-Mode Output Voltage VOS(SS) 0.3 1.6 2.1 V Figure 2 4
Change in Steady-State Common-Mode Output Voltage Between Logic States /ΔVOS(SS)/ 0 50 mV RL = 50Ω, Figure 3 4
Maximum Steady-State Open-Circuit Output Voltage A VA(OC) 0 2.4 V Figure 5 4
Maximum Steady-State Open-Circuit Output Voltage B VB(OC) 0 2.4 V Figure 5 4
Voltage Overshoot, Low-to-High Level Output VP(H) 1.2 VSS RL = 50Ω, CL = 5 pF, CD = 0.5 pF, Figure 7; specification ensured by characterization 4
Voltage Overshoot, High-to-Low Level Output VP(L) -0.2 VSS RL = 50Ω, CL = 5 pF, CD = 0.5 pF, Figure 8; specification ensured by characterization 4
Output Short-Circuit Current IOS -43 43 mA Figure 6; magnitude only 4
Driver High-Impedance Output Current IA IA 0 32 μA VA = 3.8V, VB = 1.2V 4
Driver High-Impedance Output Current IA IA -20 20 μA VA = 0V or 2.4V, VB = 1.2V 4
Driver High-Impedance Output Current IA IA -32 0 μA VA = -1.4V, VB = 1.2V 4
Driver High-Impedance Output Current IB IB 0 32 μA VA = 3.8V, VB = 1.2V 4
Driver High-Impedance Output Current IB IB -20 20 μA VA = 0V or 2.4V, VB = 1.2V 4
Driver High-Impedance Output Current IB IB -32 0 μA VA = -1.4V, VB = 1.2V 4
Driver High-Impedance Output Differential Current IAB (IA − IB) -4 4 μA VA = VB, -1.4V ≤ V ≤ 3.8V 4
Driver High-Impedance Output Power-Off Current IA(OFF) IA(OFF) 0 32 μA VA = 3.8V, VB = 1.2V, DEn = 0V, 0V ≤ VDD ≤ 1.5V 4
Driver High-Impedance Output Power-Off Current IA(OFF) IA(OFF) -20 20 μA VA = 0V or 2.4V, VB = 1.2V, DEn = 0V, 0V ≤ VDD ≤ 1.5V 4
Driver High-Impedance Output Power-Off Current IA(OFF) IA(OFF) -32 0 μA VA = -1.4V, VB = 1.2V, DEn = 0V, 0V ≤ VDD ≤ 1.5V 4
Driver High-Impedance Output Power-Off Current IB(OFF) IB(OFF) 0 32 μA VA = 3.8V, VB = 1.2V, DEn = 0V, 0V ≤ VDD ≤ 1.5V 5
Driver High-Impedance Output Power-Off Current IB(OFF) IB(OFF) -20 20 μA VA = 0V or 2.4V, VB = 1.2V, DEn = 0V, 0V ≤ VDD ≤ 1.5V 5
Driver High-Impedance Output Power-Off Current IB(OFF) IB(OFF) -32 0 μA VA = -1.4V, VB = 1.2V, DEn = 0V, 0V ≤ VDD ≤ 1.5V 5
Driver High-Impedance Output Power-Off Differential Current IAB(OFF) (IA(OFF) − IB(OFF)) -4 4 μA VA = VB, -1.4V ≤ V ≤ 3.8V, DEn = 0V, 0V ≤ VDD ≤ 1.5V 5
Loaded Supply Current Enabled ICCL 65 75 mA RL = 50Ω (All Outputs), DI = VDD or GND, DEn = VDD or GND (All Outputs) 5
No Load Supply Current Disabled ICCZ 19 24 mA DI = VDD or GND, DEn = GND (All Outputs) 5
Differential Propagation Delay High to Low tPHL 1.8 3.9 6.5 ns RL = 50Ω, CL = 5 pF, CD = 0.5 pF, Figure 7 5
Differential Propagation Delay Low to High tPLH 1.8 3.9 6.5 ns RL = 50Ω, CL = 5 pF, CD = 0.5 pF, Figure 7 5
Differential Pulse Skew tSKD1 0 25 100 ps /tPHL − tPLH/, RL = 50Ω, CL = 5 pF, CD = 0.5 pF 5
Channel-to-Channel Skew tSKD2 0 70 250 ps CL = 5 pF, CD = 0.5 pF, Figure 7 5
Differential Part-to-Part Skew (Constant TA and VDD) tSKD3 0 1.5 2 ns Figure 7 and Figure 8; same VDD and within 5°C 5
Differential Part-to-Part Skew tSKD4 0 4.7 ns Figure 7 and Figure 8 5
Rise Time tTLH 1.1 2 3 ns Figure 7 5
Fall Time tTHL 1.1 2 3 ns Figure 7 5
Disable Time High to Z tPHZ 6 11 ns RL = 50Ω, CL = 5 pF, CD = 0.5 pF, Figure 9 5
Disable Time Low to Z tPLZ 6 11 ns RL = 50Ω, CL = 5 pF, CD = 0.5 pF, Figure 9 5
Enable Time Z to High tPZH 11 ns Figure 9 5
Enable Time Z to Low tPZL 6 11 ns Figure 10 5
Maximum Operating Frequency fMAX 125 MHz 5
Package Thermal Resistance Junction-to-Ambient θJA 52 °C/W 4-Layer, 2 oz. Cu, JEDEC 3
Package Thermal Resistance Junction-to-Case θJC 19 °C/W 4-Layer, 2 oz. Cu, JEDEC 3

CAD (KiCad official)

  • Symbol: DS91M124TMAX
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ds91m124tmax-etched.step / ds91m124tmax-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds91m124tmax.step / ds91m124tmax.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 0a9a66d03d2c0804, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF