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DS91M040TSQX

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Texas Instruments LVDS ICs, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS91M040TSQX

Texas Instruments · LVDS ICs · WQFN-32-EP(5x5)

DS91M040TSQX from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RO0 tri_state Channel 0 LVCMOS receiver output; VOH ≥ 2.4 V at IOH = −8 mA, VOL ≤ 0.4 V at IOL = 8 mA; tri-stated (IOZ ≤ ±10 µA) when RE0 = H.
2 DI0 input Channel 0 LVCMOS driver input; VIH = 2.0 V min, VIL = 0.8 V max; converts LVTTL/LVCMOS logic to M-LVDS on A0/B0 when DE0 = H.
3 RO1 tri_state Channel 1 LVCMOS receiver output; VOH ≥ 2.4 V at IOH = −8 mA, VOL ≤ 0.4 V at IOL = 8 mA; tri-stated (IOZ ≤ ±10 µA) when RE1 = H.
4 DI1 input Channel 1 LVCMOS driver input; VIH = 2.0 V min, VIL = 0.8 V max; converts LVTTL/LVCMOS logic to M-LVDS on A1/B1 when DE1 = H.
5 RO2 tri_state Channel 2 LVCMOS receiver output; VOH ≥ 2.4 V at IOH = −8 mA, VOL ≤ 0.4 V at IOL = 8 mA; tri-stated (IOZ ≤ ±10 µA) when RE2 = H.
6 DI2 input Channel 2 LVCMOS driver input; VIH = 2.0 V min, VIL = 0.8 V max; converts LVTTL/LVCMOS logic to M-LVDS on A2/B2 when DE2 = H.
7 RO3 tri_state Channel 3 LVCMOS receiver output; VOH ≥ 2.4 V at IOH = −8 mA, VOL ≤ 0.4 V at IOL = 8 mA; tri-stated (IOZ ≤ ±10 µA) when RE3 = H.
8 DI3 input Channel 3 LVCMOS driver input; VIH = 2.0 V min, VIL = 0.8 V max; converts LVTTL/LVCMOS logic to M-LVDS on A3/B3 when DE3 = H.
9 FSEN2 input Failsafe receiver-type select for channels 1 and 3 with 300 kΩ internal pullup; FSEN2 = L → Type 1 thresholds (VIT± = ±50 mV), FSEN2 = H → Type 2 thresholds (VIT+ = 100-150 mV).
10 MDE input Master device enable; MDE = H powers up device, MDE = L overrides all other controls and powers down device (ICCPD = 3-5 mA); wake-up time 500 ms.
11 VDD power_in +3.3 V ± 0.3 V power supply pin; recommended operating range VDD = 3.0-3.6 V.
12 VDD power_in +3.3 V ± 0.3 V power supply pin; recommended operating range VDD = 3.0-3.6 V.
13 RE2 input Channel 2 LVCMOS receiver enable with 300 kΩ internal pullup; RE2 = L enables receiver, RE2 = H tri-states RO2 output.
14 DE2 input Channel 2 LVCMOS driver enable with 300 kΩ internal pulldown; DE2 = H enables driver, DE2 = L tri-states A2/B2 outputs.
15 RE3 input Channel 3 LVCMOS receiver enable with 300 kΩ internal pullup; RE3 = L enables receiver, RE3 = H tri-states RO3 output.
16 DE3 input Channel 3 LVCMOS driver enable with 300 kΩ internal pulldown; DE3 = H enables driver, DE3 = L tri-states A3/B3 outputs.
17 A3 bidirectional Channel 3 non-inverting M-LVDS driver output / receiver input;
18 B3 bidirectional Channel 3 inverting M-LVDS driver output / receiver input;
19 A2 bidirectional Channel 2 non-inverting M-LVDS driver output / receiver input;
20 B2 bidirectional Channel 2 inverting M-LVDS driver output / receiver input;
21 A1 bidirectional Channel 1 non-inverting M-LVDS driver output / receiver input;
22 B1 bidirectional Channel 1 inverting M-LVDS driver output / receiver input;
23 A0 bidirectional Channel 0 non-inverting M-LVDS driver output / receiver input;
24 B0 bidirectional Channel 0 inverting M-LVDS driver output / receiver input;
25 DE0 input Channel 0 LVCMOS driver enable with 300 kΩ internal pulldown; DE0 = H enables driver, DE0 = L tri-states A0/B0 outputs.
26 RE0 input Channel 0 LVCMOS receiver enable with 300 kΩ internal pullup; RE0 = L enables receiver, RE0 = H tri-states RO0 output.
27 DE1 input Channel 1 LVCMOS driver enable with 300 kΩ internal pulldown; DE1 = H enables driver, DE1 = L tri-states A1/B1 outputs.
28 RE1 input Channel 1 LVCMOS receiver enable with 300 kΩ internal pullup; RE1 = L enables receiver, RE1 = H tri-states RO1 output.
29 VDD power_in +3.3 V ± 0.3 V power supply pin; recommended operating range VDD = 3.0-3.6 V.
30 VDD power_in +3.3 V ± 0.3 V power supply pin; recommended operating range VDD = 3.0-3.6 V.
31 GND power_in Power ground pin; 0 V reference for all supply voltages.
32 FSEN1 input Failsafe receiver-type select for channels 0 and 2 with 300 kΩ internal pullup; FSEN1 = L → Type 1 thresholds (VIT± = ±50 mV), FSEN1 = H → Type 2 thresholds (VIT+ = 100-150 mV).
33 DAP power_in Exposed thermal pad, electrically GND; must be soldered to PCB ground plane for thermal and mechanical performance (θJC = 2.8 °C/W, θJA = 29.4 °C/W on 4-layer 2 oz Cu board).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-32-EP(5x5)
Category Interface
Pins 33

CAD (KiCad official)

  • Symbol: DS91M040TSQX
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ds91m040tsqx-etched.step / ds91m040tsqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds91m040tsqx.step / ds91m040tsqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 9be2a4c2c06208b6, retrieved 2026-09-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF