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DS90UR908QSQE

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Texas Instruments Serializers, Deserializers, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS90UR908QSQE

Texas Instruments · Serializers, Deserializers · WQFN-48-EP(7x7)

DS90UR908QSQE from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PDB input Power-down input with internal pull-down: PDB = 1 enables the device, and PDB = 0 powers it down with outputs TRI-STATE and control registers reset.
2 SSC[0] input Spread-spectrum clock (SSCG) range select bit 0 with internal pull-down, with the modulation settings given in Tables 5 and 6.
3 SSC[1] input Spread-spectrum clock (SSCG) range select bit 1 with internal pull-down, with the modulation settings given in Tables 5 and 6.
4 SDA bidirectional Optional serial control bus data, open drain, which requires an external pull-up resistor to VDDIO.
5 SCL input Optional serial control bus clock input, which requires an external pull-up resistor to VDDIO.
6 VDDL power_in Logic power supply, 1.8 V ±5%.
7 SSC[2] input Spread-spectrum clock (SSCG) range select bit 2 with internal pull-down, with the modulation settings given in Tables 5 and 6.
8 VDDP power_in PLL power supply, 1.8 V ±5%.
9 GND power_in Ground.
10 CONFIG[0] input Operating mode and interfacing-device select (pin or register) with internal pull-down, per Table 1.
11 CONFIG[1] input Operating mode and interfacing-device select (pin or register) with internal pull-down, per Table 1.
12 ID[x] passive Optional serial control bus device ID address select, using a resistor to ground and a 10 kΩ pull-up to the 1.8 V rail per Table 7.
13 VDDTX power_in FPD-Link output power supply, 3.3 V ±10%.
14 GND power_in Ground.
15 TxOUT3+ output True LVDS data output, bit 3 of the FPD-Link output (mapping inferred from the pin-table grouping).
16 TxOUT3- output Inverting LVDS data output, bit 3 of the FPD-Link output (mapping inferred from the pin-table grouping).
17 TxCLKOUT+ output True LVDS clock output.
18 TxCLKOUT- output Inverting LVDS clock output.
19 TxOUT2+ output True LVDS data output, bit 2 of the FPD-Link output (mapping inferred from the pin-table grouping).
20 TxOUT2- output Inverting LVDS data output, bit 2 of the FPD-Link output (mapping inferred from the pin-table grouping).
21 TxOUT1+ output True LVDS data output, bit 1 of the FPD-Link output (mapping inferred from the pin-table grouping).
22 TxOUT1- output Inverting LVDS data output, bit 1 of the FPD-Link output (mapping inferred from the pin-table grouping).
23 TxOUT0+ output True LVDS data output, bit 0 of the FPD-Link output (mapping inferred from the pin-table grouping).
24 TxOUT0- output Inverting LVDS data output, bit 0 of the FPD-Link output (mapping inferred from the pin-table grouping).
25 VDDIO power_in LVCMOS I/O power supply, either 1.8 V ±5% or 3.3 V ±10%.
26 GND power_in Ground.
27 LOCK output LVCMOS CDR lock status output: LOCK = 1 when the PLL is locked, and LOCK = 0 when unlocked, with outputs then set by OSS_SEL and OEN.
28 PASS/EQ bidirectional Shared pin: as PASS (BIST) output it is high when no errors are detected and low when errors are detected, and as the EQ strap input (read at power-up) EQ = 1 enables input equalization (~13 dB) and EQ = 0 disables it (~1.625 dB).
29 BISTEN input BIST mode enable input with internal pull-down: BISTEN = 1 enables BIST mode and BISTEN = 0 selects normal mode.
30 OEN input Output enable input with internal pull-down that controls the output states per Table 3.
31 VDDL power_in Logic power supply, 1.8 V ±5%.
32 GND power_in Ground.
33 VODSEL input FPD-Link output voltage select with internal pull-down: VODSEL = 1 gives ±400 mV (800 mVp-p typ) and VODSEL = 0 gives ±250 mV (500 mVp-p typ).
34 MAPSEL input FPD-Link map select (pin or register) with internal pull-down: MAPSEL = 1 puts the MSB on TxOUT3+/- and MAPSEL = 0 puts the LSB on TxOUT3+/-.
35 OSS_SEL input Output sleep state select input with internal pull-down that sets the output state when LOCK is low, per Table 3.
36 LFMODE input Low-frequency mode select (pin or register) with internal pull-down: LF_MODE = 1 for TxCLKOUT 5-20 MHz and LF_MODE = 0 for TxCLKOUT 20-65 MHz.
37 RES input Reserved pin with internal pull-down that must be tied low.
38 VDDA power_in Analog power supply, 1.8 V ±5%.
39 GND power_in Ground.
40 RIN+ input True FPD-Link II LVDS input, which must be AC coupled with a 100 nF capacitor and has internal termination.
41 RIN- input Inverting FPD-Link II LVDS input, which must be AC coupled with a 100 nF capacitor and has internal termination.
42 CMF passive Common-mode filter pin giving access to the internal termination center tap, where a recommended 4.7 µF or higher capacitor may be added.
43 VDDA power_in Analog power supply, 1.8 V ±5%.
44 GND power_in Ground.
45 GND power_in Ground.
46 VDDSC power_in SSC generator power supply, 1.8 V ±5%.
47 VDDSC power_in SSC generator power supply, 1.8 V ±5%.
48 GND power_in Ground.
49 DAP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48-EP(7x7)
Category Interface
Pins 49

CAD (KiCad official)

  • Symbol: DS90UR908QSQE
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds90ur908qsqe-etched.step / ds90ur908qsqe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ur908qsqe.step / ds90ur908qsqe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 5d306979dcf7176a, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF