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DS90UR905QSQ

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Texas Instruments Interface - Specialized, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS90UR905QSQ

Texas Instruments · Interface - Specialized · WQFN-48-EP(7x7)

DS90UR905QSQ from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B[6] input BLUE parallel interface data input bit 6, LVCMOS input with internal pulldown.
2 B[7] input BLUE parallel interface data input bit 7 (MSB), LVCMOS input with internal pulldown.
3 HS input Horizontal sync input; when CONFIG[1:0]=01 the pulse width must be 3 PCLKs or longer to be transmitted, and the signal is limited to 2 transitions per 130 PCLKs.
4 VS power_in Vertical sync input, limited to 1 transition per 130 PCLKs so the minimum pulse width is 130 PCLKs.
5 DE input Data enable input; when CONFIG[1:0]=01 the pulse width must be 3 PCLKs or longer to be transmitted, and the signal is limited to 2 transitions per 130 PCLKs.
6 ID[x] input Serial control bus device ID address select (analog, optional); set by resistor to ground and 10 kΩ pullup to the 1.8 V rail, see Table 11.
7 VDDL power_in Logic power, 1.8 V ±5%.
8 SCL input Serial control bus clock input (optional); requires an external pullup resistor to VDDIO.
9 SDA bidirectional Serial control bus data input/output (optional, open-drain); requires an external pullup resistor to VDDIO.
10 PCLK input Pixel clock input; data and control are latched on the edge set by the RFB function.
11 RFB input Pixel clock input latch edge select: RFB=1 latches on the rising edge, RFB=0 latches on the falling edge.
12 CONFIG[0] input Operating mode select bit (with CONFIG[1]): 00 = DS90UR906Q with control filter disabled, 01 = DS90UR906Q with control filter enabled, 10 = DS90UR124/DS99R124, 11 = DS90C124.
13 CONFIG[1] input Operating mode select bit (with CONFIG[0]), selecting the interfacing device and control-signal filter as listed for CONFIG[0].
14 VDDP power_in PLL power, 1.8 V ±5%.
15 RES0 input Reserved; tie LOW.
16 RES1 input Reserved; tie LOW.
17 VDDHS power_in TX high-speed logic power, 1.8 V ±5%.
18 RES2 input Reserved; tie LOW.
19 DOUT- output LVDS inverting output; must be AC-coupled with a 100 nF capacitor.
20 DOUT+ output LVDS true output; must be AC-coupled with a 100 nF capacitor.
21 PDB input Power-down input: PDB=1 enables the serializer, PDB=0 powers it down (DOUT± driven high, PLL shut down, control registers reset); the VDD ramp must be faster than 1.5 ms or a PDB capacitor is needed.
22 VDDTX power_in Output driver power, 1.8 V ±5%.
23 De-Emph input De-emphasis control (analog, pullup): leave open to disable, or tie a resistor to GND (or set by register) to enable de-emphasis.
24 VODSEL input Differential output voltage select: VODSEL=1 gives LVDS VOD ±420 mV (840 mVp-p typical) for long cable/de-emphasis, VODSEL=0 gives 280 mV (560 mVp-p typical).
25 R[0] input RED parallel interface data input bit 0 (LSB), LVCMOS input with internal pulldown.
26 R[1] input RED parallel interface data input bit 1, LVCMOS input with internal pulldown.
27 R[2] input RED parallel interface data input bit 2, LVCMOS input with internal pulldown.
28 R[3] input RED parallel interface data input bit 3, LVCMOS input with internal pulldown.
29 R[4] input RED parallel interface data input bit 4, LVCMOS input with internal pulldown.
30 VDDIO power_in LVCMOS I/O power, 1.8 V ±5% or 3.3 V ±10%.
31 BISTEN input BIST mode enable input: BISTEN=1 enables BIST, BISTEN=0 disables it.
32 R[5] input RED parallel interface data input bit 5, LVCMOS input with internal pulldown.
33 R[6] input RED parallel interface data input bit 6, LVCMOS input with internal pulldown.
34 R[7] input RED parallel interface data input bit 7 (MSB), LVCMOS input with internal pulldown.
35 G[0] input GREEN parallel interface data input bit 0 (LSB), LVCMOS input with internal pulldown.
36 G[1] input GREEN parallel interface data input bit 1, LVCMOS input with internal pulldown.
37 G[2] input GREEN parallel interface data input bit 2, LVCMOS input with internal pulldown.
38 G[3] input GREEN parallel interface data input bit 3, LVCMOS input with internal pulldown.
39 G[4] input GREEN parallel interface data input bit 4, LVCMOS input with internal pulldown.
40 G[5] input GREEN parallel interface data input bit 5, LVCMOS input with internal pulldown.
41 G[6] input GREEN parallel interface data input bit 6, LVCMOS input with internal pulldown.
42 G[7] input GREEN parallel interface data input bit 7 (MSB), LVCMOS input with internal pulldown.
43 B[0] input BLUE parallel interface data input bit 0 (LSB), LVCMOS input with internal pulldown.
44 B[1] input BLUE parallel interface data input bit 1, LVCMOS input with internal pulldown.
45 B[2] input BLUE parallel interface data input bit 2, LVCMOS input with internal pulldown.
46 B[3] input BLUE parallel interface data input bit 3, LVCMOS input with internal pulldown.
47 B[4] input BLUE parallel interface data input bit 4, LVCMOS input with internal pulldown.
48 B[5] input BLUE parallel interface data input bit 5, LVCMOS input with internal pulldown.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48-EP(7x7)
Category Interface
Pins 49

CAD (KiCad official)

  • Symbol: DS90UR905QSQ
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds90ur905qsq-etched.step / ds90ur905qsq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ur905qsq.step / ds90ur905qsq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (62 pp, sha256 5ae7d7e1acca07b7, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF