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DS90UR241IVS

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Texas Instruments Serializers, Deserializers, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS90UR241IVS

Texas Instruments · Serializers, Deserializers · TQFP-48(7x7)

DS90UR241IVS from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIN[20] input Serializer parallel LVCMOS data input DIN[20]; tie low if unused and do not leave floating.
2 DIN[21] input Serializer parallel LVCMOS data input DIN[21]; tie low if unused and do not leave floating.
3 DIN[22] input Serializer parallel LVCMOS data input DIN[22]; tie low if unused and do not leave floating.
4 DIN[23] input Serializer parallel LVCMOS data input DIN[23]; tie low if unused and do not leave floating.
5 RES0 input Reserved pin that must be connected to low level.
6 VSS power_in Digital ground for the serializer logic.
7 VDD power_in Digital 3.3V supply for the serializer logic (VDD range 3.0 V to 3.6 V).
8 RES0 input Reserved pin that must be connected to low level.
9 TPWDNB input Transmitter power-down: high enables the transmitter; low puts it in sleep mode with LVDS outputs tri-stated and PLL off.
10 TCLK input Parallel interface transmit clock input (5 MHz to 43 MHz); data is strobed on the edge selected by TRFB.
11 TRFB input Transmitter clock edge select: high strobes parallel data on the rising TCLK edge, low on the falling edge.
12 RAOFF input Randomizer control: high selects DS90C124 backward-compatible mode, low (default) enables additional randomization (2E7 LFSR).
13 RES0 input Reserved pin that must be connected to low level.
14 VDD power_in 3.3V analog supply for the PLL.
15 VSS power_in Analog ground for the PLL.
16 VDD power_in 3.3V analog supply for the VCO.
17 VSS power_in Analog ground for the VCO.
18 DEN input Transmitter data enable: high enables the LVDS driver outputs; low disables them and tri-states DOUT±, while the PLL keeps running and locked to TCLK.
19 DOUT- output LVDS inverting serial output; must drive a 100 Ω load and be AC-coupled through a 100 nF capacitor.
20 DOUT+ output LVDS non-inverting serial output; must drive a 100 Ω load and be AC-coupled through a 100 nF capacitor.
21 VSS power_in Analog ground for the LVDS output driver.
22 VDD power_in 3.3V analog supply for the LVDS output driver.
23 PRE input Pre-emphasis level select: leave unconnected to disable pre-emphasis; an external resistor RPRE to VSS (minimum 6 kΩ, Imax = 48/RPRE) enables it.
24 VODSEL input LVDS VOD select: low gives ±500 mV (RL = 100 Ω) for normal applications, high gives ±900 mV for long cables.
25 DIN[0] input Serializer parallel LVCMOS data input DIN[0]; tie low if unused and do not leave floating.
26 DIN[1] input Serializer parallel LVCMOS data input DIN[1]; tie low if unused and do not leave floating.
27 DIN[2] input Serializer parallel LVCMOS data input DIN[2]; tie low if unused and do not leave floating.
28 DIN[3] input Serializer parallel LVCMOS data input DIN[3]; tie low if unused and do not leave floating.
29 DIN[4] input Serializer parallel LVCMOS data input DIN[4]; tie low if unused and do not leave floating.
30 VDD power_in 3.3V digital supply for the serializer input/logic.
31 VSS power_in Digital ground for the serializer.
32 DIN[5] input Serializer parallel LVCMOS data input DIN[5]; tie low if unused and do not leave floating.
33 DIN[6] input Serializer parallel LVCMOS data input DIN[6]; tie low if unused and do not leave floating.
34 DIN[7] input Serializer parallel LVCMOS data input DIN[7]; tie low if unused and do not leave floating.
35 DIN[8] input Serializer parallel LVCMOS data input DIN[8]; tie low if unused and do not leave floating.
36 DIN[9] input Serializer parallel LVCMOS data input DIN[9]; tie low if unused and do not leave floating.
37 DIN[10] input Serializer parallel LVCMOS data input DIN[10]; tie low if unused and do not leave floating.
38 DIN[11] input Serializer parallel LVCMOS data input DIN[11]; tie low if unused and do not leave floating.
39 DIN[12] input Serializer parallel LVCMOS data input DIN[12]; tie low if unused and do not leave floating.
40 DIN[13] input Serializer parallel LVCMOS data input DIN[13]; tie low if unused and do not leave floating.
41 DIN[14] input Serializer parallel LVCMOS data input DIN[14]; tie low if unused and do not leave floating.
42 VDD power_in 3.3V digital supply for the serializer parallel input.
43 VSS power_in Digital ground for the serializer parallel input.
44 DIN[15] input Serializer parallel LVCMOS data input DIN[15]; tie low if unused and do not leave floating.
45 DIN[16] input Serializer parallel LVCMOS data input DIN[16]; tie low if unused and do not leave floating.
46 DIN[17] input Serializer parallel LVCMOS data input DIN[17]; tie low if unused and do not leave floating.
47 DIN[18] input Serializer parallel LVCMOS data input DIN[18]; tie low if unused and do not leave floating.
48 DIN[19] input Serializer parallel LVCMOS data input DIN[19]; tie low if unused and do not leave floating.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Interface
Pins 48

CAD (KiCad official)

  • Symbol: DS90UR241IVS
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds90ur241ivs-etched.step / ds90ur241ivs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ur241ivs.step / ds90ur241ivs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 2c3e737f4c06180d, retrieved 2026-10-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF