DS90UB962WRTDRQ1

Texas Instruments · LVDS ICs · VQFN-64(9x9)

DS90UB962WRTDRQ1 from Texas Instruments, in a VQFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD18_P3	power_in	1.8-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended for the pin group.
2	VDD18_P2	power_in	1.8-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended for the pin group.
3	PDB	input	Inverted power-down input (3.3-V tolerant) with an internal 50-kΩ pulldown; PDB = 1.8 V enables the device and PDB = 0 V powers it down, and PDB should stay low until supplies reach minimum levels.
4	RES	passive	Reserved pin that must be tied to GND for normal operation.
5	REFCLK	input	Reference clock input for a 23-MHz to 26-MHz LVCMOS oscillator (±100 ppm); 25 MHz is required for 400-Mbps, 800-Mbps or 1.6-Gbps CSI-2 data rates.
6	INTB	output	Active-low open-drain interrupt output controlled by the status registers; recommend a 4.7-kΩ pullup to 1.8 V or 3.3 V, or leave as No Connect if unused.
7	I2C_SDA2	bidirectional	Secondary I2C data open-drain I/O; pull up to VDDIO per SLVA689, or leave unconnected if unused.
8	I2C_SCL2	bidirectional	Secondary I2C clock open-drain I/O; pull up to VDDIO per SLVA689, or leave unconnected if unused.
9	GPIO0	bidirectional	General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused.
10	GPIO1	bidirectional	General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused.
11	I2C_SDA	bidirectional	Primary I2C data open-drain I/O; pull up to VDDIO per SLVA689, or leave unconnected if unused.
12	I2C_SCL	bidirectional	Primary I2C clock open-drain I/O; pull up to VDDIO per SLVA689, or leave unconnected if unused.
13	VDDL1	power_in	1.1-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended.
14	GPIO2	bidirectional	General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused.
15	GPIO3	bidirectional	General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused.
16	VDDIO	power_in	1.8-V (±5%) or 3.3-V (±10%) LVCMOS I/O power supply; requires 1-µF and 0.1-µF or 0.01-µF capacitors to GND.
17	GPIO4	bidirectional	General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused.
18	GPIO5	bidirectional	General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused.
19	GPIO6	bidirectional	General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused.
20	GPIO7	bidirectional	General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused.
21	VDD_CSI	power_in	1.1-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended.
22	CSI_CLKN	output	Negative leg of the CSI-2 differential clock output; leave as No Connect if unused.
23	CSI_CLKP	output	Positive leg of the CSI-2 differential clock output; leave as No Connect if unused.
24	CSI_D0N	output	Negative leg of CSI-2 TX differential data lane 0, controlled by the CSI_PORT_SEL, CSI_CTL and CSI_CTL2 registers; leave as No Connect if unused.
25	CSI_D0P	output	Positive leg of CSI-2 TX differential data lane 0, controlled by the CSI_PORT_SEL, CSI_CTL and CSI_CTL2 registers; leave as No Connect if unused.
26	CSI_D1N	output	Negative leg of CSI-2 TX differential data lane 1; leave as No Connect if unused.
27	CSI_D1P	output	Positive leg of CSI-2 TX differential data lane 1; leave as No Connect if unused.
28	CSI_D2N	output	Negative leg of CSI-2 TX differential data lane 2; leave as No Connect if unused.
29	CSI_D2P	output	Positive leg of CSI-2 TX differential data lane 2; leave as No Connect if unused.
30	CSI_D3N	output	Negative leg of CSI-2 TX differential data lane 3; leave as No Connect if unused.
31	CSI_D3P	output	Positive leg of CSI-2 TX differential data lane 3; leave as No Connect if unused.
32	VDD18A	power_in	1.8-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended.
33	VDD_CSI	power_in	1.1-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended.
34	NC	unconnected	No-connect pin; leave unconnected.
35	NC	unconnected	No-connect pin; leave unconnected.
36	NC	unconnected	No-connect pin; leave unconnected.
37	NC	unconnected	No-connect pin; leave unconnected.
38	NC	unconnected	No-connect pin; leave unconnected.
39	NC	unconnected	No-connect pin; leave unconnected.
40	NC	unconnected	No-connect pin; leave unconnected.
41	NC	unconnected	No-connect pin; leave unconnected.
42	NC	unconnected	No-connect pin; leave unconnected.
43	NC	unconnected	No-connect pin; leave unconnected.
44	VDDL2	power_in	1.1-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended.
45	MODE	input	Mode-select strap input; set with a pullup to VDD18 and a pulldown to GND voltage divider per the strap configuration table (Table 7-2).
46	IDX	input	I2C serial control bus device ID address strap; set with a pullup to VDD18 and a pulldown to GND voltage divider per Table 7-18.
47	VDD18_P1	power_in	1.8-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended.
48	VDD18_P0	power_in	1.8-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended.
49	VDD18_FPD0	power_in	1.8-V (±5%) power supply for FPD-Link III RX Port 0; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended.
50	RIN0+	bidirectional	Positive FPD-Link III RX Port 0 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 0 to 0 and leave as No Connect if unused.
51	RIN0-	bidirectional	Negative FPD-Link III RX Port 0 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 0 to 0 and leave as No Connect if unused.
52	VDD_FPD1	power_in	1.1-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended.
53	RIN1+	bidirectional	Positive FPD-Link III RX Port 1 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 1 to 0 and leave as No Connect if unused.
54	RIN1-	bidirectional	Negative FPD-Link III RX Port 1 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 1 to 0 and leave as No Connect if unused.
55	VDD18_FPD1	power_in	1.8-V (±5%) power supply for FPD-Link III RX Port 1; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended.
56	CMLOUTP	output	Positive channel monitor loop-through driver output; route to a test point or pad with a 100-Ω termination between CMLOUTP and CMLOUTN (recommended).
57	CMLOUTN	output	Negative channel monitor loop-through driver output; route to a test point or pad with a 100-Ω termination between CMLOUTP and CMLOUTN (recommended).
58	VDD18_FPD2	power_in	1.8-V (±5%) power supply for FPD-Link III RX Port 2; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended.
59	RIN2+	bidirectional	Positive FPD-Link III RX Port 2 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 2 to 0 and leave as No Connect if unused.
60	RIN2-	bidirectional	Negative FPD-Link III RX Port 2 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 2 to 0 and leave as No Connect if unused.
61	VDD_FPD2	power_in	1.1-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended.
62	RIN3+	bidirectional	Positive FPD-Link III RX Port 3 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 3 to 0 and leave as No Connect if unused.
63	RIN3-	bidirectional	Negative FPD-Link III RX Port 3 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 3 to 0 and leave as No Connect if unused.
64	VDD18_FPD3	power_in	1.8-V (±5%) power supply for FPD-Link III RX Port 3; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended.
65	GND	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-64(9x9)
Category	Interface
Pins	65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VDD11 (VDD_CSI, VDDL1, VDDL2, VDD_FPD1, VDD_FPD2)	VDD11	-0.3		1.32	V	Also < V(VDD18)	8
Supply voltage VDD18 (VDD18_P0-P3, VDD18A, VDD18_FPD0-FPD3)	VDD18	-0.3		2.16	V		8
VDDIO supply voltage	VDDIO	-0.3		3.96	V		8
FPD-Link III input voltage (RIN0+ to RIN3-)		-0.3		2.75	V	Device powered up (all supplies within recommended operating conditions)	8
FPD-Link III input voltage (RIN0+ to RIN3-)		-0.3		1.45	V	Device powered down, transient voltage	8
FPD-Link III input voltage (RIN0+ to RIN3-)		-0.3		1.35	V	Device powered down, DC voltage	8
CSI-2 voltage (CSI_D0P to CSI_CLKN)		-0.3		1.32	V		8
LVCMOS IO voltage (PDB)	PDB	-0.3		3.96	V		8
Open-drain voltage (I2C_SDA, I2C_SCL, I2C_SDA2, I2C_SCL2, INTB)		-0.3		3.96	V		8
NC voltage (No Connect pins 34-43)		-0.3		1.32	V		8
Junction temperature				150	°C		8
Storage temperature	Tstg	-65		150	°C		8
Supply voltage V(VDD11)	V(VDD11)	1.045	1.1	1.155	V		8
Supply voltage V(VDD18)	V(VDD18)	1.71	1.8	1.89	V		8
LVCMOS I/O supply voltage V(VDDIO)	V(VDDIO)	1.71	1.8	1.89	V	V(VDDIO) = 1.8 V	8
LVCMOS I/O supply voltage V(VDDIO)	V(VDDIO)	3	3.3	3.6	V	V(VDDIO) = 3.3 V	8
Open-drain voltage	V(INTB), V(I2C)	1.71		3.6	V	INTB = V(INTB), I2C pins = V(I2C)	8
Operating free-air temperature	TA	-40	25	105	°C		8
MIPI data rate (per CSI-2 lane)		368	800	1664	Mbps		9
MIPI CSI-2 HS clock frequency		184	400	832	MHz		9
Reference clock frequency (REFCLK)		23	25	26	MHz		9
Spread-spectrum REFCLK modulation percentage, center spread		-0.5		0.5	%	REFCLK, center spread	9
Spread-spectrum REFCLK modulation percentage, down spread		-1		0	%	REFCLK, down spread	9
Total power consumption in operation mode	PT		800	999	mW	CSI-2 TX 4 data lanes + CLK at 1.664 Gbps; 4 x FPD-Link III RX at 4.16 Gbps; CSI-2 mode, default registers	9
Deserializer supply current VDD11 (includes load current)	IDDT1		165	310	mA	CSI-2 TX 4 data lanes + CLK at 1.664 Gbps; 4 x FPD-Link III RX at 4.16 Gbps; CSI-2 mode, default registers	10
Deserializer supply current VDD18 (includes load current)	IDDT1		295	340	mA	CSI-2 TX 4 data lanes + CLK at 1.664 Gbps; 4 x FPD-Link III RX at 4.16 Gbps; CSI-2 mode, default registers	10
Deserializer supply current VDDIO (includes load current)	IDDT1		2	3	mA	CSI-2 TX 4 data lanes + CLK at 1.664 Gbps; 4 x FPD-Link III RX at 4.16 Gbps; CSI-2 mode, default registers	10
Deserializer supply current VDD11 (includes load current)	IDDT2		122	300	mA	CSI-2 TX 1.664 Gbps; FPD-Link III line rate 1.867 Gbps; RAW12 HF mode, default registers	10
Deserializer supply current VDD18 (includes load current)	IDDT2		263	305	mA	CSI-2 TX 1.664 Gbps; FPD-Link III line rate 1.867 Gbps; RAW12 HF mode, default registers	10
Low level output voltage (GPIO[7:0], INTB), 1.8 V LVCMOS	VOL			0.45	V	IOL = 2 mA, V(VDDIO) = 1.71 to 1.89 V	10
High level input current, 1.8 V LVCMOS	IIH	45		115	μA	VIN = V(VDDIO) = 1.71 to 1.89 V, internal pulldown enabled (GPIO[7:0], PDB)	10
Low level input current, 1.8 V LVCMOS	IIL	-20		3.5	μA	VIN = 0 V (GPIO[7:0], PDB, REFCLK)	10
Strap pin input current	IIN-STRAP	-1		1	μA	VIN = 0 V to V(VDD18) (MODE, IDX)	10
TRI-STATE output current, 1.8 V LVCMOS	IOZ	-20		20	μA	VOUT = 0 V or V(VDDIO), PDB = LOW (GPIO[7:0])	10
High level output voltage, 3.3 V LVCMOS	VOH	2.4			V	IOH = -4 mA, V(VDDIO) = 3.0 to 3.6 V (GPIO[7:0])	10
Low level output voltage (GPIO[7:0], INTB), 3.3 V LVCMOS	VOL			0.4	V	IOL = 4 mA, V(VDDIO) = 3.0 to 3.6 V	10
High level input voltage GPIO[7:0], REFCLK, 3.3 V LVCMOS	VIH	2			V	V(VDDIO) = 3.0 to 3.6 V	10
High level input voltage PDB, 3.3 V LVCMOS	VIH	1.17			V	V(VDDIO) = 3.0 to 3.6 V	10
Low level input voltage GPIO[7:0], REFCLK, 3.3 V LVCMOS	VIL			0.8	V	V(VDDIO) = 3.0 to 3.6 V	10
Low level input voltage PDB, 3.3 V LVCMOS	VIL			0.63	V	V(VDDIO) = 3.0 to 3.6 V	10
High level input current, 3.3 V LVCMOS	IIH	85		215	μA	VIN = V(VDDIO) = 3.0 to 3.6 V, internal pulldown enabled (GPIO[7:0], PDB)	10
Low level input current, 3.3 V LVCMOS	IIL	-20		3.5	μA	VIN = V(VDDIO) = 0 V (GPIO[7:0], PDB, REFCLK)	11
TRI-STATE output current, 3.3 V LVCMOS	IOZ	-20		30	μA	VOUT = 0 V or V(VDDIO), PDB = LOW (GPIO[7:0])	11
Output low level, I2C (VOL1)	VOL1	0		0.4	V	V(I2C) = 3.0 to 3.6 V, IOL = 3 mA, Standard-mode and Fast-mode	11
Input current, I2C	IIN	-10		10	μA	VIN = 0 V or V(I2C)	11
Internal termination resistance, single-ended	RT	40	50	60	Ω	Single-ended RIN+ or RIN-	11
Internal termination resistance, differential	RT	80	100	120	Ω	Differential across RIN+ and RIN-	11
Back channel single-ended output voltage	VOUT-BC	190	220	260	mV	RL = 50 Ω, coaxial configuration, forward channel disabled	11
Back channel differential output voltage	VOD-BC	380	440	520	mV	RL = 100 Ω, STP configuration, forward channel disabled	11
Back channel frequency fBC	fBC	46		56	Mbps	CSI-2 synchronous mode, no REFCLK	14
HS data rate HSTXDBR	HSTXDBR	400	800	1600	Mbps	REFCLK = 25 MHz (CSI_D0P to CSI_D3N)	14
UI instantaneous	UIINST	0.6		2.7	ns	1, 2, 3, or 4 lane configuration; data rate 368 Mbps to 1.664 Gbps	16
Clock lane HS entry tCLK-PREPARE	tCLK-PREPARE	38		95	ns	Clock lane HS entry	16
Thermal resistance, junction-to-ambient	RθJA		23.8		°C/W		9
Thermal resistance, junction-to-case (top)	RθJC(TOP)		10.4		°C/W		9
Thermal resistance, junction-to-case (bottom)	RθJC(BOT)		0.4		°C/W		9
Thermal resistance, junction-to-board	RθJB		7.6		°C/W		9
Junction-to-top characterization parameter	ψJT		0.1		°C/W		9
Junction-to-board characterization parameter	ψJB		7.5		°C/W		9

CAD (KiCad official)

Symbol: DS90UB962WRTDRQ1
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: VQFN-64(9x9) (KiCad packages3D, STEP)
3D model files: ds90ub962wrtdrq1-etched.step / ds90ub962wrtdrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub962wrtdrq1.step / ds90ub962wrtdrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (182 pp, sha256 71e8e30ebaf93244, retrieved 2026-10-18, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# DS90UB962WRTDRQ1

**Texas Instruments** · LVDS ICs · VQFN-64(9x9)

DS90UB962WRTDRQ1 from Texas Instruments, in a VQFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD18_P3 | power_in | 1.8-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended for the pin group. |
| 2 | VDD18_P2 | power_in | 1.8-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended for the pin group. |
| 3 | PDB | input | Inverted power-down input (3.3-V tolerant) with an internal 50-kΩ pulldown; PDB = 1.8 V enables the device and PDB = 0 V powers it down, and PDB should stay low until supplies reach minimum levels. |
| 4 | RES | passive | Reserved pin that must be tied to GND for normal operation. |
| 5 | REFCLK | input | Reference clock input for a 23-MHz to 26-MHz LVCMOS oscillator (±100 ppm); 25 MHz is required for 400-Mbps, 800-Mbps or 1.6-Gbps CSI-2 data rates. |
| 6 | INTB | output | Active-low open-drain interrupt output controlled by the status registers; recommend a 4.7-kΩ pullup to 1.8 V or 3.3 V, or leave as No Connect if unused. |
| 7 | I2C_SDA2 | bidirectional | Secondary I2C data open-drain I/O; pull up to VDDIO per SLVA689, or leave unconnected if unused. |
| 8 | I2C_SCL2 | bidirectional | Secondary I2C clock open-drain I/O; pull up to VDDIO per SLVA689, or leave unconnected if unused. |
| 9 | GPIO0 | bidirectional | General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused. |
| 10 | GPIO1 | bidirectional | General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused. |
| 11 | I2C_SDA | bidirectional | Primary I2C data open-drain I/O; pull up to VDDIO per SLVA689, or leave unconnected if unused. |
| 12 | I2C_SCL | bidirectional | Primary I2C clock open-drain I/O; pull up to VDDIO per SLVA689, or leave unconnected if unused. |
| 13 | VDDL1 | power_in | 1.1-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended. |
| 14 | GPIO2 | bidirectional | General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused. |
| 15 | GPIO3 | bidirectional | General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused. |
| 16 | VDDIO | power_in | 1.8-V (±5%) or 3.3-V (±10%) LVCMOS I/O power supply; requires 1-µF and 0.1-µF or 0.01-µF capacitors to GND. |
| 17 | GPIO4 | bidirectional | General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused. |
| 18 | GPIO5 | bidirectional | General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused. |
| 19 | GPIO6 | bidirectional | General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused. |
| 20 | GPIO7 | bidirectional | General-purpose I/O, disabled at power-up with a 25-kΩ typical internal pulldown; leave as No Connect if unused. |
| 21 | VDD_CSI | power_in | 1.1-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended. |
| 22 | CSI_CLKN | output | Negative leg of the CSI-2 differential clock output; leave as No Connect if unused. |
| 23 | CSI_CLKP | output | Positive leg of the CSI-2 differential clock output; leave as No Connect if unused. |
| 24 | CSI_D0N | output | Negative leg of CSI-2 TX differential data lane 0, controlled by the CSI_PORT_SEL, CSI_CTL and CSI_CTL2 registers; leave as No Connect if unused. |
| 25 | CSI_D0P | output | Positive leg of CSI-2 TX differential data lane 0, controlled by the CSI_PORT_SEL, CSI_CTL and CSI_CTL2 registers; leave as No Connect if unused. |
| 26 | CSI_D1N | output | Negative leg of CSI-2 TX differential data lane 1; leave as No Connect if unused. |
| 27 | CSI_D1P | output | Positive leg of CSI-2 TX differential data lane 1; leave as No Connect if unused. |
| 28 | CSI_D2N | output | Negative leg of CSI-2 TX differential data lane 2; leave as No Connect if unused. |
| 29 | CSI_D2P | output | Positive leg of CSI-2 TX differential data lane 2; leave as No Connect if unused. |
| 30 | CSI_D3N | output | Negative leg of CSI-2 TX differential data lane 3; leave as No Connect if unused. |
| 31 | CSI_D3P | output | Positive leg of CSI-2 TX differential data lane 3; leave as No Connect if unused. |
| 32 | VDD18A | power_in | 1.8-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended. |
| 33 | VDD_CSI | power_in | 1.1-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended. |
| 34 | NC | unconnected | No-connect pin; leave unconnected. |
| 35 | NC | unconnected | No-connect pin; leave unconnected. |
| 36 | NC | unconnected | No-connect pin; leave unconnected. |
| 37 | NC | unconnected | No-connect pin; leave unconnected. |
| 38 | NC | unconnected | No-connect pin; leave unconnected. |
| 39 | NC | unconnected | No-connect pin; leave unconnected. |
| 40 | NC | unconnected | No-connect pin; leave unconnected. |
| 41 | NC | unconnected | No-connect pin; leave unconnected. |
| 42 | NC | unconnected | No-connect pin; leave unconnected. |
| 43 | NC | unconnected | No-connect pin; leave unconnected. |
| 44 | VDDL2 | power_in | 1.1-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended. |
| 45 | MODE | input | Mode-select strap input; set with a pullup to VDD18 and a pulldown to GND voltage divider per the strap configuration table (Table 7-2). |
| 46 | IDX | input | I2C serial control bus device ID address strap; set with a pullup to VDD18 and a pulldown to GND voltage divider per Table 7-18. |
| 47 | VDD18_P1 | power_in | 1.8-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended. |
| 48 | VDD18_P0 | power_in | 1.8-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended. |
| 49 | VDD18_FPD0 | power_in | 1.8-V (±5%) power supply for FPD-Link III RX Port 0; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended. |
| 50 | RIN0+ | bidirectional | Positive FPD-Link III RX Port 0 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 0 to 0 and leave as No Connect if unused. |
| 51 | RIN0- | bidirectional | Negative FPD-Link III RX Port 0 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 0 to 0 and leave as No Connect if unused. |
| 52 | VDD_FPD1 | power_in | 1.1-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended. |
| 53 | RIN1+ | bidirectional | Positive FPD-Link III RX Port 1 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 1 to 0 and leave as No Connect if unused. |
| 54 | RIN1- | bidirectional | Negative FPD-Link III RX Port 1 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 1 to 0 and leave as No Connect if unused. |
| 55 | VDD18_FPD1 | power_in | 1.8-V (±5%) power supply for FPD-Link III RX Port 1; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended. |
| 56 | CMLOUTP | output | Positive channel monitor loop-through driver output; route to a test point or pad with a 100-Ω termination between CMLOUTP and CMLOUTN (recommended). |
| 57 | CMLOUTN | output | Negative channel monitor loop-through driver output; route to a test point or pad with a 100-Ω termination between CMLOUTP and CMLOUTN (recommended). |
| 58 | VDD18_FPD2 | power_in | 1.8-V (±5%) power supply for FPD-Link III RX Port 2; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended. |
| 59 | RIN2+ | bidirectional | Positive FPD-Link III RX Port 2 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 2 to 0 and leave as No Connect if unused. |
| 60 | RIN2- | bidirectional | Negative FPD-Link III RX Port 2 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 2 to 0 and leave as No Connect if unused. |
| 61 | VDD_FPD2 | power_in | 1.1-V (±5%) power supply; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended. |
| 62 | RIN3+ | bidirectional | Positive FPD-Link III RX Port 3 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 3 to 0 and leave as No Connect if unused. |
| 63 | RIN3- | bidirectional | Negative FPD-Link III RX Port 3 input (AC-coupled per Table 8-4) that receives forward-channel video/control and transmits back-channel data; set RX_PORT_CTL bit 3 to 0 and leave as No Connect if unused. |
| 64 | VDD18_FPD3 | power_in | 1.8-V (±5%) power supply for FPD-Link III RX Port 3; requires 0.1-µF or 0.01-µF capacitors to GND at each VDD pin, with additional 1-µF and 10-µF decoupling recommended. |
| 65 | GND | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64(9x9) |
| Category | Interface |
| Pins | 65 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD11 (VDD_CSI, VDDL1, VDDL2, VDD_FPD1, VDD_FPD2) | VDD11 | -0.3 |  | 1.32 | V | Also < V(VDD18) | 8 |
| Supply voltage VDD18 (VDD18_P0-P3, VDD18A, VDD18_FPD0-FPD3) | VDD18 | -0.3 |  | 2.16 | V |  | 8 |
| VDDIO supply voltage | VDDIO | -0.3 |  | 3.96 | V |  | 8 |
| FPD-Link III input voltage (RIN0+ to RIN3-) |  | -0.3 |  | 2.75 | V | Device powered up (all supplies within recommended operating conditions) | 8 |
| FPD-Link III input voltage (RIN0+ to RIN3-) |  | -0.3 |  | 1.45 | V | Device powered down, transient voltage | 8 |
| FPD-Link III input voltage (RIN0+ to RIN3-) |  | -0.3 |  | 1.35 | V | Device powered down, DC voltage | 8 |
| CSI-2 voltage (CSI_D0P to CSI_CLKN) |  | -0.3 |  | 1.32 | V |  | 8 |
| LVCMOS IO voltage (PDB) | PDB | -0.3 |  | 3.96 | V |  | 8 |
| Open-drain voltage (I2C_SDA, I2C_SCL, I2C_SDA2, I2C_SCL2, INTB) |  | -0.3 |  | 3.96 | V |  | 8 |
| NC voltage (No Connect pins 34-43) |  | -0.3 |  | 1.32 | V |  | 8 |
| Junction temperature |  |  |  | 150 | °C |  | 8 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 8 |
| Supply voltage V(VDD11) | V(VDD11) | 1.045 | 1.1 | 1.155 | V |  | 8 |
| Supply voltage V(VDD18) | V(VDD18) | 1.71 | 1.8 | 1.89 | V |  | 8 |
| LVCMOS I/O supply voltage V(VDDIO) | V(VDDIO) | 1.71 | 1.8 | 1.89 | V | V(VDDIO) = 1.8 V | 8 |
| LVCMOS I/O supply voltage V(VDDIO) | V(VDDIO) | 3 | 3.3 | 3.6 | V | V(VDDIO) = 3.3 V | 8 |
| Open-drain voltage | V(INTB), V(I2C) | 1.71 |  | 3.6 | V | INTB = V(INTB), I2C pins = V(I2C) | 8 |
| Operating free-air temperature | TA | -40 | 25 | 105 | °C |  | 8 |
| MIPI data rate (per CSI-2 lane) |  | 368 | 800 | 1664 | Mbps |  | 9 |
| MIPI CSI-2 HS clock frequency |  | 184 | 400 | 832 | MHz |  | 9 |
| Reference clock frequency (REFCLK) |  | 23 | 25 | 26 | MHz |  | 9 |
| Spread-spectrum REFCLK modulation percentage, center spread |  | -0.5 |  | 0.5 | % | REFCLK, center spread | 9 |
| Spread-spectrum REFCLK modulation percentage, down spread |  | -1 |  | 0 | % | REFCLK, down spread | 9 |
| Total power consumption in operation mode | PT |  | 800 | 999 | mW | CSI-2 TX 4 data lanes + CLK at 1.664 Gbps; 4 x FPD-Link III RX at 4.16 Gbps; CSI-2 mode, default registers | 9 |
| Deserializer supply current VDD11 (includes load current) | IDDT1 |  | 165 | 310 | mA | CSI-2 TX 4 data lanes + CLK at 1.664 Gbps; 4 x FPD-Link III RX at 4.16 Gbps; CSI-2 mode, default registers | 10 |
| Deserializer supply current VDD18 (includes load current) | IDDT1 |  | 295 | 340 | mA | CSI-2 TX 4 data lanes + CLK at 1.664 Gbps; 4 x FPD-Link III RX at 4.16 Gbps; CSI-2 mode, default registers | 10 |
| Deserializer supply current VDDIO (includes load current) | IDDT1 |  | 2 | 3 | mA | CSI-2 TX 4 data lanes + CLK at 1.664 Gbps; 4 x FPD-Link III RX at 4.16 Gbps; CSI-2 mode, default registers | 10 |
| Deserializer supply current VDD11 (includes load current) | IDDT2 |  | 122 | 300 | mA | CSI-2 TX 1.664 Gbps; FPD-Link III line rate 1.867 Gbps; RAW12 HF mode, default registers | 10 |
| Deserializer supply current VDD18 (includes load current) | IDDT2 |  | 263 | 305 | mA | CSI-2 TX 1.664 Gbps; FPD-Link III line rate 1.867 Gbps; RAW12 HF mode, default registers | 10 |
| Low level output voltage (GPIO[7:0], INTB), 1.8 V LVCMOS | VOL |  |  | 0.45 | V | IOL = 2 mA, V(VDDIO) = 1.71 to 1.89 V | 10 |
| High level input current, 1.8 V LVCMOS | IIH | 45 |  | 115 | μA | VIN = V(VDDIO) = 1.71 to 1.89 V, internal pulldown enabled (GPIO[7:0], PDB) | 10 |
| Low level input current, 1.8 V LVCMOS | IIL | -20 |  | 3.5 | μA | VIN = 0 V (GPIO[7:0], PDB, REFCLK) | 10 |
| Strap pin input current | IIN-STRAP | -1 |  | 1 | μA | VIN = 0 V to V(VDD18) (MODE, IDX) | 10 |
| TRI-STATE output current, 1.8 V LVCMOS | IOZ | -20 |  | 20 | μA | VOUT = 0 V or V(VDDIO), PDB = LOW (GPIO[7:0]) | 10 |
| High level output voltage, 3.3 V LVCMOS | VOH | 2.4 |  |  | V | IOH = -4 mA, V(VDDIO) = 3.0 to 3.6 V (GPIO[7:0]) | 10 |
| Low level output voltage (GPIO[7:0], INTB), 3.3 V LVCMOS | VOL |  |  | 0.4 | V | IOL = 4 mA, V(VDDIO) = 3.0 to 3.6 V | 10 |
| High level input voltage GPIO[7:0], REFCLK, 3.3 V LVCMOS | VIH | 2 |  |  | V | V(VDDIO) = 3.0 to 3.6 V | 10 |
| High level input voltage PDB, 3.3 V LVCMOS | VIH | 1.17 |  |  | V | V(VDDIO) = 3.0 to 3.6 V | 10 |
| Low level input voltage GPIO[7:0], REFCLK, 3.3 V LVCMOS | VIL |  |  | 0.8 | V | V(VDDIO) = 3.0 to 3.6 V | 10 |
| Low level input voltage PDB, 3.3 V LVCMOS | VIL |  |  | 0.63 | V | V(VDDIO) = 3.0 to 3.6 V | 10 |
| High level input current, 3.3 V LVCMOS | IIH | 85 |  | 215 | μA | VIN = V(VDDIO) = 3.0 to 3.6 V, internal pulldown enabled (GPIO[7:0], PDB) | 10 |
| Low level input current, 3.3 V LVCMOS | IIL | -20 |  | 3.5 | μA | VIN = V(VDDIO) = 0 V (GPIO[7:0], PDB, REFCLK) | 11 |
| TRI-STATE output current, 3.3 V LVCMOS | IOZ | -20 |  | 30 | μA | VOUT = 0 V or V(VDDIO), PDB = LOW (GPIO[7:0]) | 11 |
| Output low level, I2C (VOL1) | VOL1 | 0 |  | 0.4 | V | V(I2C) = 3.0 to 3.6 V, IOL = 3 mA, Standard-mode and Fast-mode | 11 |
| Input current, I2C | IIN | -10 |  | 10 | μA | VIN = 0 V or V(I2C) | 11 |
| Internal termination resistance, single-ended | RT | 40 | 50 | 60 | Ω | Single-ended RIN+ or RIN- | 11 |
| Internal termination resistance, differential | RT | 80 | 100 | 120 | Ω | Differential across RIN+ and RIN- | 11 |
| Back channel single-ended output voltage | VOUT-BC | 190 | 220 | 260 | mV | RL = 50 Ω, coaxial configuration, forward channel disabled | 11 |
| Back channel differential output voltage | VOD-BC | 380 | 440 | 520 | mV | RL = 100 Ω, STP configuration, forward channel disabled | 11 |
| Back channel frequency fBC | fBC | 46 |  | 56 | Mbps | CSI-2 synchronous mode, no REFCLK | 14 |
| HS data rate HSTXDBR | HSTXDBR | 400 | 800 | 1600 | Mbps | REFCLK = 25 MHz (CSI_D0P to CSI_D3N) | 14 |
| UI instantaneous | UIINST | 0.6 |  | 2.7 | ns | 1, 2, 3, or 4 lane configuration; data rate 368 Mbps to 1.664 Gbps | 16 |
| Clock lane HS entry tCLK-PREPARE | tCLK-PREPARE | 38 |  | 95 | ns | Clock lane HS entry | 16 |
| Thermal resistance, junction-to-ambient | RθJA |  | 23.8 |  | °C/W |  | 9 |
| Thermal resistance, junction-to-case (top) | RθJC(TOP) |  | 10.4 |  | °C/W |  | 9 |
| Thermal resistance, junction-to-case (bottom) | RθJC(BOT) |  | 0.4 |  | °C/W |  | 9 |
| Thermal resistance, junction-to-board | RθJB |  | 7.6 |  | °C/W |  | 9 |
| Junction-to-top characterization parameter | ψJT |  | 0.1 |  | °C/W |  | 9 |
| Junction-to-board characterization parameter | ψJB |  | 7.5 |  | °C/W |  | 9 |

## CAD (KiCad official)

- Symbol: `DS90UB962WRTDRQ1`
- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`
- 3D model: VQFN-64(9x9) (KiCad packages3D, STEP)
- 3D model files: `ds90ub962wrtdrq1-etched.step` / `ds90ub962wrtdrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds90ub962wrtdrq1.step` / `ds90ub962wrtdrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds90ub962-q1) (182 pp, sha256 `71e8e30ebaf93244`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ds90ub962wrtdrq1-datasheet.pdf)