component
DS90UB960WRTDTQ1
Public Made by Adomby adom
Texas Instruments LVDS ICs, VQFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DS90UB960WRTDTQ1
Texas Instruments · LVDS ICs · VQFN-64(9x9)
DS90UB960WRTDTQ1 from Texas Instruments, in a VQFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD18_P3 | power_in | 1.8-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended for the pin group. |
| 2 | VDD18_P2 | power_in | 1.8-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended for the pin group. |
| 3 | PDB | input | Inverted power-down input with internal 50-kΩ pulldown; PDB must be held low until supplies reach minimum levels, is 3.3-V tolerant, and high (1.8 V) enables the device. |
| 4 | RES | passive | This pin must be tied to GND for normal operation. |
| 5 | REFCLK | input | Reference clock oscillator input, typically 23-MHz to 26-MHz LVCMOS (100 ppm); 25 MHz is required for 400 Mbps, 800 Mbps, 1.2 Gbps or 1.6 Gbps CSI-2 data rates. |
| 6 | INTB | output | Active-low open-drain interrupt output controlled by status registers; recommend 4.7-kΩ pullup to 1.8 V or 3.3 V, or leave as No Connect if unused. |
| 7 | I2C_SDA2 | bidirectional | Secondary I2C data open-drain input/output; pull up to VDDIO per SLVA689, or leave unconnected if unused. |
| 8 | I2C_SCL2 | bidirectional | Secondary I2C clock open-drain input/output; pull up to VDDIO per SLVA689, or leave unconnected if unused. |
| 9 | GPIO0 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 10 | GPIO1 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 11 | I2C_SDA | bidirectional | Primary I2C data open-drain input/output; pull up to VDDIO per SLVA689, or leave unconnected if unused. |
| 12 | I2C_SCL | bidirectional | Primary I2C clock open-drain input/output; pull up to VDDIO per SLVA689, or leave unconnected if unused. |
| 13 | VDDL1 | power_in | 1.1-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 14 | GPIO2 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 15 | GPIO3 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 16 | VDDIO | power_in | 1.8-V (±5%) or 3.3-V (±10%) LVCMOS I/O power; requires 1-μF and 0.1-μF or 0.01-μF capacitors to GND. |
| 17 | GPIO4 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 18 | GPIO5 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 19 | GPIO6 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 20 | GPIO7 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 21 | VDD_CSI0 | power_in | 1.1-V (±5%) power supply for CSI-2 Port 0; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 22 | CSI0_CLKN | output | CSI-2 TX Port 0 differential clock output (negative); leave as No Connect if unused. |
| 23 | CSI0_CLKP | output | CSI-2 TX Port 0 differential clock output (positive); leave as No Connect if unused. |
| 24 | CSI0_D0N | output | CSI-2 TX Port 0 differential data lane 0 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 25 | CSI0_D0P | output | CSI-2 TX Port 0 differential data lane 0 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 26 | CSI0_D1N | output | CSI-2 TX Port 0 differential data lane 1 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 27 | CSI0_D1P | output | CSI-2 TX Port 0 differential data lane 1 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 28 | CSI0_D2N | output | CSI-2 TX Port 0 differential data lane 2 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 29 | CSI0_D2P | output | CSI-2 TX Port 0 differential data lane 2 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 30 | CSI0_D3N | output | CSI-2 TX Port 0 differential data lane 3 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 31 | CSI0_D3P | output | CSI-2 TX Port 0 differential data lane 3 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 32 | VDD18A | power_in | 1.8-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 33 | VDD_CSI1 | power_in | 1.1-V (±5%) power supply for CSI-2 Port 1; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 34 | CSI1_CLKN | output | CSI-2 TX Port 1 differential clock output (negative); leave as No Connect if unused. |
| 35 | CSI1_CLKP | output | CSI-2 TX Port 1 differential clock output (positive); leave as No Connect if unused. |
| 36 | CSI1_D0N | output | CSI-2 TX Port 1 differential data lane 0 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 37 | CSI1_D0P | output | CSI-2 TX Port 1 differential data lane 0 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 38 | CSI1_D1N | output | CSI-2 TX Port 1 differential data lane 1 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 39 | CSI1_D1P | output | CSI-2 TX Port 1 differential data lane 1 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 40 | CSI1_D2N | output | CSI-2 TX Port 1 differential data lane 2 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 41 | CSI1_D2P | output | CSI-2 TX Port 1 differential data lane 2 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 42 | CSI1_D3N | output | CSI-2 TX Port 1 differential data lane 3 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 43 | CSI1_D3P | output | CSI-2 TX Port 1 differential data lane 3 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 44 | VDDL2 | power_in | 1.1-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 45 | MODE | input | Mode select strap input; connect a pullup to VDD18 and a pulldown to GND as a voltage divider per Table 7-2. |
| 46 | IDX | input | I2C serial control bus device ID address strap input; connect a pullup to VDD18 and a pulldown to GND as a voltage divider per Table 7-18. |
| 47 | VDD18_P1 | power_in | 1.8-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 48 | VDD18_P0 | power_in | 1.8-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 49 | VDD18_FPD0 | power_in | 1.8-V (±5%) power supply for FPD-Link III RX Port 0; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 50 | RIN0+ | bidirectional | FPD-Link III RX Port 0 positive input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 0 set to 0 disables the port if unused. |
| 51 | RIN0- | bidirectional | FPD-Link III RX Port 0 negative input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 0 set to 0 disables the port if unused. |
| 52 | VDD_FPD1 | power_in | 1.1-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 53 | RIN1+ | bidirectional | FPD-Link III RX Port 1 positive input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 1 set to 0 disables the port if unused. |
| 54 | RIN1- | bidirectional | FPD-Link III RX Port 1 negative input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 1 set to 0 disables the port if unused. |
| 55 | VDD18_FPD1 | power_in | 1.8-V (±5%) power supply for FPD-Link III RX Port 1; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 56 | CMLOUTP | output | Channel Monitor Loop-through driver positive differential output; route to a test point or pad with 100-Ω termination between CMLOUTP and CMLOUTN (recommended). |
| 57 | CMLOUTN | output | Channel Monitor Loop-through driver negative differential output; route to a test point or pad with 100-Ω termination between CMLOUTP and CMLOUTN (recommended). |
| 58 | VDD18_FPD2 | power_in | 1.8-V (±5%) power supply for FPD-Link III RX Port 2; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 59 | RIN2+ | bidirectional | FPD-Link III RX Port 2 positive input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 2 set to 0 disables the port if unused. |
| 60 | RIN2- | bidirectional | FPD-Link III RX Port 2 negative input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 2 set to 0 disables the port if unused. |
| 61 | VDD_FPD2 | power_in | 1.1-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 62 | RIN3+ | bidirectional | FPD-Link III RX Port 3 positive input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 3 set to 0 disables the port if unused. |
| 63 | RIN3- | bidirectional | FPD-Link III RX Port 3 negative input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 3 set to 0 disables the port if unused. |
| 64 | VDD18_FPD3 | power_in | 1.8-V (±5%) power supply for FPD-Link III RX Port 3; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64(9x9) |
| Category | Communication Interface Chip |
| Pins | 65 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD11 (VDD_CSI0, VDD_CSI1, VDDL1, VDDL2, VDD_FPD1, VDD_FPD2) | VDD11 | -0.3 | 1.32 | V | and <V(VDD18) | 8 | |
| Supply voltage VDD18 (VDD18_P0, VDD18_P1, VDD18_P2, VDD18_P3, VDD18A, VDD18_FPD0-3) | VDD18 | -0.3 | 2.16 | V | 8 | ||
| Supply voltage VDDIO | VDDIO | -0.3 | 3.96 | V | 8 | ||
| FPD-Link III input voltage RIN0+/- to RIN3+/- | -0.3 | 2.75 | V | Device powered up (All supplies within recommended operating conditions) | 8 | ||
| FPD-Link III input voltage RIN0+/- to RIN3+/- | -0.3 | 1.45 | V | Device powered down, Transient voltage | 8 | ||
| FPD-Link III input voltage RIN0+/- to RIN3+/- | -0.3 | 1.35 | V | Device powered down, DC voltage | 8 | ||
| CSI-2 voltage (CSI0_ and CSI1_ D/CLK P/N pins) | -0.3 | 1.32 | V | 8 | |||
| LVCMOS IO voltage PDB | PDB | -0.3 | 3.96 | V | 8 | ||
| LVCMOS IO voltage GPIO[7:0], REFCLK, RES, CMLOUTP, CMLOUTN (upper limit printed as V(VDDIO) + 0.3 V) | -0.3 | V | 8 | ||||
| Configuration input voltage MODE, IDX (upper limit printed as V(VDD18) + 0.3 V) | -0.3 | V | 8 | ||||
| Open-drain voltage I2C_SDA, I2C_SCL, I2C_SDA2, I2C_SCL2, INTB | -0.3 | 3.96 | V | 8 | |||
| Junction temperature | Tj | 150 | °C | 8 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 8 | ||
| Supply voltage V(VDD11) | V(VDD11) | 1.045 | 1.1 | 1.155 | V | 9 | |
| Supply voltage V(VDD18) | V(VDD18) | 1.71 | 1.8 | 1.89 | V | 9 | |
| LVCMOS I/O supply voltage V(VDDIO) | V(VDDIO) | 1.71 | 1.8 | 1.89 | V | V(VDDIO) = 1.8 V | 9 |
| LVCMOS I/O supply voltage V(VDDIO) | V(VDDIO) | 3 | 3.3 | 3.6 | V | V(VDDIO) = 3.3 V | 9 |
| Open-drain voltage | V(INTB), V(I2C) | 1.71 | 3.6 | V | INTB = V(INTB), I2C pins = V(I2C) | 9 | |
| Operating free-air temperature | TA | -40 | 25 | 105 | °C | 9 | |
| MIPI data rate (per CSI-2 lane) | 368 | 800 | 1664 | Mbps | 9 | ||
| MIPI CSI-2 HS clock frequency | 184 | 400 | 832 | MHz | 9 | ||
| Reference clock frequency | REFCLK | 23 | 25 | 26 | MHz | 9 | |
| Spread-spectrum reference clock modulation percentage | -0.5 | 0.5 | % | REFCLK, Center spread | 9 | ||
| Spread-spectrum reference clock modulation percentage | -1 | 0 | % | REFCLK, Down spread | 9 | ||
| Local I2C frequency | fI2C | 1 | MHz | 9 | |||
| Supply noise V(VDD11) | 25 | mVP-P | DC to 50 MHz | 9 | |||
| Supply noise V(VDD18) | 50 | mVP-P | DC to 50 MHz | 9 | |||
| Supply noise V(VDDIO) = 1.8 V | 50 | mVP-P | DC to 50 MHz | 9 | |||
| Supply noise V(VDDIO) = 3.3 V | 100 | mVP-P | DC to 50 MHz | 9 | |||
| Supply noise RIN0+, RIN1+, RIN2+, RIN3+ | 10 | mVP-P | DC to 50 MHz | 9 | |||
| Total power consumption in operation mode | PT | 800 | 999 | mW | CSI-2 TX = 2 x (4 data lanes + 1 CLK lane), 1.664 Gbps; 4 x FPD-Link III RX, 4.16 Gbps; CSI-2 non-replicate; default registers | 9 | |
| Deserializer supply current VDD11 (includes load current) | IDDT1 | 165 | 310 | mA | CSI-2 TX = 4 data lanes + 1 CLK lane, 1.664 Gbps; 4 x FPD-Link III RX, 4.16 Gbps; CSI-2 non-replicate; default registers | 10 | |
| Deserializer supply current VDD18 (includes load current) | IDDT1 | 295 | 340 | mA | CSI-2 TX = 4 data lanes + 1 CLK lane, 1.664 Gbps; 4 x FPD-Link III RX, 4.16 Gbps; CSI-2 non-replicate; default registers | 10 | |
| Deserializer supply current VDDIO (includes load current) | IDDT1 | 2 | 3 | mA | CSI-2 TX = 4 data lanes + 1 CLK lane, 1.664 Gbps; 4 x FPD-Link III RX, 4.16 Gbps; CSI-2 non-replicate; default registers | 10 | |
| Deserializer supply current VDD11 (includes load current) | IDDT2 | 174 | 360 | mA | CSI-2 TX = 2 x (4 data lanes + 1 CLK lane), 1.664 Gbps; 4 x FPD-Link III RX, 4.16 Gbps; CSI-2 replicate; default registers | 10 | |
| Deserializer supply current VDD18 (includes load current) | IDDT2 | 312 | 370 | mA | CSI-2 TX = 2 x (4 data lanes + 1 CLK lane), 1.664 Gbps; 4 x FPD-Link III RX, 4.16 Gbps; CSI-2 replicate; default registers | 10 | |
| Deserializer shutdown current VDD11 | IDDZ | 160 | mA | PDB = LOW | 10 | ||
| Deserializer shutdown current VDD18 | IDDZ | 4 | mA | PDB = LOW | 10 | ||
| Low level output voltage (1.8-V LVCMOS) | VOL | 0.45 | V | IOL = 2 mA, V(VDDIO) = 1.71 to 1.89 V; GPIO[7:0], INTB | 10 | ||
| Low level output voltage (3.3-V LVCMOS) | VOL | 0.4 | V | IOL = 4 mA, V(VDDIO) = 3.0 to 3.6 V; GPIO[7:0], INTB | 11 | ||
| High level output voltage (3.3-V LVCMOS) | VOH | 2.4 | V | IOH = -4 mA, V(VDDIO) = 3.0 to 3.6 V; GPIO[7:0] | 11 | ||
| High level input voltage (3.3-V LVCMOS) GPIO[7:0], REFCLK | VIH | 2 | V | V(VDDIO) = 3.0 to 3.6 V | 11 | ||
| Low level input voltage (3.3-V LVCMOS) GPIO[7:0], REFCLK | VIL | 0.8 | V | V(VDDIO) = 3.0 to 3.6 V | 11 | ||
| High level input voltage (3.3-V LVCMOS) PDB | VIH | 1.17 | V | V(VDDIO) = 3.0 to 3.6 V | 11 | ||
| Low level input voltage (3.3-V LVCMOS) PDB | VIL | 0.63 | V | V(VDDIO) = 3.0 to 3.6 V | 11 | ||
| LVCMOS low-to-high transition time GPIO[7:0] | tCLH | 2.5 | ns | V(VDDIO) = 1.71 to 1.89 V or 3.0 to 3.6 V; CL = 8 pF (lumped load); Default Registers | 13 | ||
| LVCMOS high-to-low transition time GPIO[7:0] | tCHL | 2.5 | ns | V(VDDIO) = 1.71 to 1.89 V or 3.0 to 3.6 V; CL = 8 pF (lumped load); Default Registers | 13 | ||
| PDB reset pulse width | tPDB | 2 | ms | Power supplies applied and stable | 13 | ||
| Internal termination resistance, single-ended RIN+ or RIN- | RT | 40 | 50 | 60 | Ω | Single-ended RIN+ or RIN- | 11 |
| Internal termination resistance, differential across RIN+ and RIN- | RT | 80 | 100 | 120 | Ω | Differential across RIN+ and RIN- | 11 |
| HS transmit static common-mode voltage | VCMTX | 150 | 200 | 250 | mV | CSI0/CSI1 D0-D3 and CLK P/N pins | 12 |
| HS transmit differential voltage | /VOD/ | 140 | 200 | 270 | mV | CSI0/CSI1 D0-D3 and CLK P/N pins | 12 |
| HS output high voltage | VOHHS | 360 | mV | 12 | |||
| Junction-to-ambient thermal resistance | RθJA | 23.8 | °C/W | 9 | |||
| Junction-to-case (top) thermal resistance | RθJC(TOP) | 10.4 | °C/W | 9 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(BOT) | 0.4 | °C/W | 9 | |||
| Junction-to-board thermal resistance | RθJB | 7.6 | °C/W | 9 | |||
| Junction-to-top characterization parameter | ψJT | 0.1 | °C/W | 9 | |||
| Junction-to-board characterization parameter | ψJB | 7.5 | °C/W | 9 |
CAD (KiCad official)
- Symbol:
DS90UB960WRTDTQ1 - Footprint:
Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm - 3D model: VQFN-64(9x9) (KiCad packages3D, STEP)
- 3D model files:
ds90ub960wrtdtq1-etched.step/ds90ub960wrtdtq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds90ub960wrtdtq1.step/ds90ub960wrtdtq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (191 pp, sha256
60c8314e70121607, retrieved 2026-10-28, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DS90UB960WRTDTQ1
**Texas Instruments** · LVDS ICs · VQFN-64(9x9)
DS90UB960WRTDTQ1 from Texas Instruments, in a VQFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD18_P3 | power_in | 1.8-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended for the pin group. |
| 2 | VDD18_P2 | power_in | 1.8-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended for the pin group. |
| 3 | PDB | input | Inverted power-down input with internal 50-kΩ pulldown; PDB must be held low until supplies reach minimum levels, is 3.3-V tolerant, and high (1.8 V) enables the device. |
| 4 | RES | passive | This pin must be tied to GND for normal operation. |
| 5 | REFCLK | input | Reference clock oscillator input, typically 23-MHz to 26-MHz LVCMOS (100 ppm); 25 MHz is required for 400 Mbps, 800 Mbps, 1.2 Gbps or 1.6 Gbps CSI-2 data rates. |
| 6 | INTB | output | Active-low open-drain interrupt output controlled by status registers; recommend 4.7-kΩ pullup to 1.8 V or 3.3 V, or leave as No Connect if unused. |
| 7 | I2C_SDA2 | bidirectional | Secondary I2C data open-drain input/output; pull up to VDDIO per SLVA689, or leave unconnected if unused. |
| 8 | I2C_SCL2 | bidirectional | Secondary I2C clock open-drain input/output; pull up to VDDIO per SLVA689, or leave unconnected if unused. |
| 9 | GPIO0 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 10 | GPIO1 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 11 | I2C_SDA | bidirectional | Primary I2C data open-drain input/output; pull up to VDDIO per SLVA689, or leave unconnected if unused. |
| 12 | I2C_SCL | bidirectional | Primary I2C clock open-drain input/output; pull up to VDDIO per SLVA689, or leave unconnected if unused. |
| 13 | VDDL1 | power_in | 1.1-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 14 | GPIO2 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 15 | GPIO3 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 16 | VDDIO | power_in | 1.8-V (±5%) or 3.3-V (±10%) LVCMOS I/O power; requires 1-μF and 0.1-μF or 0.01-μF capacitors to GND. |
| 17 | GPIO4 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 18 | GPIO5 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 19 | GPIO6 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 20 | GPIO7 | bidirectional | General-purpose I/O with 25-kΩ typical internal pulldown, disabled at power-up; leave as No Connect if unused. |
| 21 | VDD_CSI0 | power_in | 1.1-V (±5%) power supply for CSI-2 Port 0; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 22 | CSI0_CLKN | output | CSI-2 TX Port 0 differential clock output (negative); leave as No Connect if unused. |
| 23 | CSI0_CLKP | output | CSI-2 TX Port 0 differential clock output (positive); leave as No Connect if unused. |
| 24 | CSI0_D0N | output | CSI-2 TX Port 0 differential data lane 0 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 25 | CSI0_D0P | output | CSI-2 TX Port 0 differential data lane 0 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 26 | CSI0_D1N | output | CSI-2 TX Port 0 differential data lane 1 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 27 | CSI0_D1P | output | CSI-2 TX Port 0 differential data lane 1 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 28 | CSI0_D2N | output | CSI-2 TX Port 0 differential data lane 2 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 29 | CSI0_D2P | output | CSI-2 TX Port 0 differential data lane 2 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 30 | CSI0_D3N | output | CSI-2 TX Port 0 differential data lane 3 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 31 | CSI0_D3P | output | CSI-2 TX Port 0 differential data lane 3 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 32 | VDD18A | power_in | 1.8-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 33 | VDD_CSI1 | power_in | 1.1-V (±5%) power supply for CSI-2 Port 1; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 34 | CSI1_CLKN | output | CSI-2 TX Port 1 differential clock output (negative); leave as No Connect if unused. |
| 35 | CSI1_CLKP | output | CSI-2 TX Port 1 differential clock output (positive); leave as No Connect if unused. |
| 36 | CSI1_D0N | output | CSI-2 TX Port 1 differential data lane 0 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 37 | CSI1_D0P | output | CSI-2 TX Port 1 differential data lane 0 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 38 | CSI1_D1N | output | CSI-2 TX Port 1 differential data lane 1 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 39 | CSI1_D1P | output | CSI-2 TX Port 1 differential data lane 1 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 40 | CSI1_D2N | output | CSI-2 TX Port 1 differential data lane 2 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 41 | CSI1_D2P | output | CSI-2 TX Port 1 differential data lane 2 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 42 | CSI1_D3N | output | CSI-2 TX Port 1 differential data lane 3 output (negative), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 43 | CSI1_D3P | output | CSI-2 TX Port 1 differential data lane 3 output (positive), configured via CSI_PORT_SEL, CSI_CTL and CSI_CTL2; leave as No Connect if unused. |
| 44 | VDDL2 | power_in | 1.1-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 45 | MODE | input | Mode select strap input; connect a pullup to VDD18 and a pulldown to GND as a voltage divider per Table 7-2. |
| 46 | IDX | input | I2C serial control bus device ID address strap input; connect a pullup to VDD18 and a pulldown to GND as a voltage divider per Table 7-18. |
| 47 | VDD18_P1 | power_in | 1.8-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 48 | VDD18_P0 | power_in | 1.8-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 49 | VDD18_FPD0 | power_in | 1.8-V (±5%) power supply for FPD-Link III RX Port 0; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 50 | RIN0+ | bidirectional | FPD-Link III RX Port 0 positive input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 0 set to 0 disables the port if unused. |
| 51 | RIN0- | bidirectional | FPD-Link III RX Port 0 negative input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 0 set to 0 disables the port if unused. |
| 52 | VDD_FPD1 | power_in | 1.1-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 53 | RIN1+ | bidirectional | FPD-Link III RX Port 1 positive input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 1 set to 0 disables the port if unused. |
| 54 | RIN1- | bidirectional | FPD-Link III RX Port 1 negative input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 1 set to 0 disables the port if unused. |
| 55 | VDD18_FPD1 | power_in | 1.8-V (±5%) power supply for FPD-Link III RX Port 1; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 56 | CMLOUTP | output | Channel Monitor Loop-through driver positive differential output; route to a test point or pad with 100-Ω termination between CMLOUTP and CMLOUTN (recommended). |
| 57 | CMLOUTN | output | Channel Monitor Loop-through driver negative differential output; route to a test point or pad with 100-Ω termination between CMLOUTP and CMLOUTN (recommended). |
| 58 | VDD18_FPD2 | power_in | 1.8-V (±5%) power supply for FPD-Link III RX Port 2; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 59 | RIN2+ | bidirectional | FPD-Link III RX Port 2 positive input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 2 set to 0 disables the port if unused. |
| 60 | RIN2- | bidirectional | FPD-Link III RX Port 2 negative input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 2 set to 0 disables the port if unused. |
| 61 | VDD_FPD2 | power_in | 1.1-V (±5%) power supply pin; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 62 | RIN3+ | bidirectional | FPD-Link III RX Port 3 positive input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 3 set to 0 disables the port if unused. |
| 63 | RIN3- | bidirectional | FPD-Link III RX Port 3 negative input; must be AC-coupled per Table 8-4, and RX_PORT_CTL bit 3 set to 0 disables the port if unused. |
| 64 | VDD18_FPD3 | power_in | 1.8-V (±5%) power supply for FPD-Link III RX Port 3; requires 0.1-μF or 0.01-μF capacitor to GND at each VDD pin, with additional 1-μF and 10-μF decoupling recommended. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64(9x9) |
| Category | Communication Interface Chip |
| Pins | 65 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD11 (VDD_CSI0, VDD_CSI1, VDDL1, VDDL2, VDD_FPD1, VDD_FPD2) | VDD11 | -0.3 | | 1.32 | V | and <V(VDD18) | 8 |
| Supply voltage VDD18 (VDD18_P0, VDD18_P1, VDD18_P2, VDD18_P3, VDD18A, VDD18_FPD0-3) | VDD18 | -0.3 | | 2.16 | V | | 8 |
| Supply voltage VDDIO | VDDIO | -0.3 | | 3.96 | V | | 8 |
| FPD-Link III input voltage RIN0+/- to RIN3+/- | | -0.3 | | 2.75 | V | Device powered up (All supplies within recommended operating conditions) | 8 |
| FPD-Link III input voltage RIN0+/- to RIN3+/- | | -0.3 | | 1.45 | V | Device powered down, Transient voltage | 8 |
| FPD-Link III input voltage RIN0+/- to RIN3+/- | | -0.3 | | 1.35 | V | Device powered down, DC voltage | 8 |
| CSI-2 voltage (CSI0_ and CSI1_ D/CLK P/N pins) | | -0.3 | | 1.32 | V | | 8 |
| LVCMOS IO voltage PDB | PDB | -0.3 | | 3.96 | V | | 8 |
| LVCMOS IO voltage GPIO[7:0], REFCLK, RES, CMLOUTP, CMLOUTN (upper limit printed as V(VDDIO) + 0.3 V) | | -0.3 | | | V | | 8 |
| Configuration input voltage MODE, IDX (upper limit printed as V(VDD18) + 0.3 V) | | -0.3 | | | V | | 8 |
| Open-drain voltage I2C_SDA, I2C_SCL, I2C_SDA2, I2C_SCL2, INTB | | -0.3 | | 3.96 | V | | 8 |
| Junction temperature | Tj | | | 150 | °C | | 8 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 8 |
| Supply voltage V(VDD11) | V(VDD11) | 1.045 | 1.1 | 1.155 | V | | 9 |
| Supply voltage V(VDD18) | V(VDD18) | 1.71 | 1.8 | 1.89 | V | | 9 |
| LVCMOS I/O supply voltage V(VDDIO) | V(VDDIO) | 1.71 | 1.8 | 1.89 | V | V(VDDIO) = 1.8 V | 9 |
| LVCMOS I/O supply voltage V(VDDIO) | V(VDDIO) | 3 | 3.3 | 3.6 | V | V(VDDIO) = 3.3 V | 9 |
| Open-drain voltage | V(INTB), V(I2C) | 1.71 | | 3.6 | V | INTB = V(INTB), I2C pins = V(I2C) | 9 |
| Operating free-air temperature | TA | -40 | 25 | 105 | °C | | 9 |
| MIPI data rate (per CSI-2 lane) | | 368 | 800 | 1664 | Mbps | | 9 |
| MIPI CSI-2 HS clock frequency | | 184 | 400 | 832 | MHz | | 9 |
| Reference clock frequency | REFCLK | 23 | 25 | 26 | MHz | | 9 |
| Spread-spectrum reference clock modulation percentage | | -0.5 | | 0.5 | % | REFCLK, Center spread | 9 |
| Spread-spectrum reference clock modulation percentage | | -1 | | 0 | % | REFCLK, Down spread | 9 |
| Local I2C frequency | fI2C | | | 1 | MHz | | 9 |
| Supply noise V(VDD11) | | | | 25 | mVP-P | DC to 50 MHz | 9 |
| Supply noise V(VDD18) | | | | 50 | mVP-P | DC to 50 MHz | 9 |
| Supply noise V(VDDIO) = 1.8 V | | | | 50 | mVP-P | DC to 50 MHz | 9 |
| Supply noise V(VDDIO) = 3.3 V | | | | 100 | mVP-P | DC to 50 MHz | 9 |
| Supply noise RIN0+, RIN1+, RIN2+, RIN3+ | | | | 10 | mVP-P | DC to 50 MHz | 9 |
| Total power consumption in operation mode | PT | | 800 | 999 | mW | CSI-2 TX = 2 x (4 data lanes + 1 CLK lane), 1.664 Gbps; 4 x FPD-Link III RX, 4.16 Gbps; CSI-2 non-replicate; default registers | 9 |
| Deserializer supply current VDD11 (includes load current) | IDDT1 | | 165 | 310 | mA | CSI-2 TX = 4 data lanes + 1 CLK lane, 1.664 Gbps; 4 x FPD-Link III RX, 4.16 Gbps; CSI-2 non-replicate; default registers | 10 |
| Deserializer supply current VDD18 (includes load current) | IDDT1 | | 295 | 340 | mA | CSI-2 TX = 4 data lanes + 1 CLK lane, 1.664 Gbps; 4 x FPD-Link III RX, 4.16 Gbps; CSI-2 non-replicate; default registers | 10 |
| Deserializer supply current VDDIO (includes load current) | IDDT1 | | 2 | 3 | mA | CSI-2 TX = 4 data lanes + 1 CLK lane, 1.664 Gbps; 4 x FPD-Link III RX, 4.16 Gbps; CSI-2 non-replicate; default registers | 10 |
| Deserializer supply current VDD11 (includes load current) | IDDT2 | | 174 | 360 | mA | CSI-2 TX = 2 x (4 data lanes + 1 CLK lane), 1.664 Gbps; 4 x FPD-Link III RX, 4.16 Gbps; CSI-2 replicate; default registers | 10 |
| Deserializer supply current VDD18 (includes load current) | IDDT2 | | 312 | 370 | mA | CSI-2 TX = 2 x (4 data lanes + 1 CLK lane), 1.664 Gbps; 4 x FPD-Link III RX, 4.16 Gbps; CSI-2 replicate; default registers | 10 |
| Deserializer shutdown current VDD11 | IDDZ | | | 160 | mA | PDB = LOW | 10 |
| Deserializer shutdown current VDD18 | IDDZ | | | 4 | mA | PDB = LOW | 10 |
| Low level output voltage (1.8-V LVCMOS) | VOL | | | 0.45 | V | IOL = 2 mA, V(VDDIO) = 1.71 to 1.89 V; GPIO[7:0], INTB | 10 |
| Low level output voltage (3.3-V LVCMOS) | VOL | | | 0.4 | V | IOL = 4 mA, V(VDDIO) = 3.0 to 3.6 V; GPIO[7:0], INTB | 11 |
| High level output voltage (3.3-V LVCMOS) | VOH | 2.4 | | | V | IOH = -4 mA, V(VDDIO) = 3.0 to 3.6 V; GPIO[7:0] | 11 |
| High level input voltage (3.3-V LVCMOS) GPIO[7:0], REFCLK | VIH | 2 | | | V | V(VDDIO) = 3.0 to 3.6 V | 11 |
| Low level input voltage (3.3-V LVCMOS) GPIO[7:0], REFCLK | VIL | | | 0.8 | V | V(VDDIO) = 3.0 to 3.6 V | 11 |
| High level input voltage (3.3-V LVCMOS) PDB | VIH | 1.17 | | | V | V(VDDIO) = 3.0 to 3.6 V | 11 |
| Low level input voltage (3.3-V LVCMOS) PDB | VIL | | | 0.63 | V | V(VDDIO) = 3.0 to 3.6 V | 11 |
| LVCMOS low-to-high transition time GPIO[7:0] | tCLH | | | 2.5 | ns | V(VDDIO) = 1.71 to 1.89 V or 3.0 to 3.6 V; CL = 8 pF (lumped load); Default Registers | 13 |
| LVCMOS high-to-low transition time GPIO[7:0] | tCHL | | | 2.5 | ns | V(VDDIO) = 1.71 to 1.89 V or 3.0 to 3.6 V; CL = 8 pF (lumped load); Default Registers | 13 |
| PDB reset pulse width | tPDB | 2 | | | ms | Power supplies applied and stable | 13 |
| Internal termination resistance, single-ended RIN+ or RIN- | RT | 40 | 50 | 60 | Ω | Single-ended RIN+ or RIN- | 11 |
| Internal termination resistance, differential across RIN+ and RIN- | RT | 80 | 100 | 120 | Ω | Differential across RIN+ and RIN- | 11 |
| HS transmit static common-mode voltage | VCMTX | 150 | 200 | 250 | mV | CSI0/CSI1 D0-D3 and CLK P/N pins | 12 |
| HS transmit differential voltage | /VOD/ | 140 | 200 | 270 | mV | CSI0/CSI1 D0-D3 and CLK P/N pins | 12 |
| HS output high voltage | VOHHS | | | 360 | mV | | 12 |
| Junction-to-ambient thermal resistance | RθJA | | 23.8 | | °C/W | | 9 |
| Junction-to-case (top) thermal resistance | RθJC(TOP) | | 10.4 | | °C/W | | 9 |
| Junction-to-case (bottom) thermal resistance | RθJC(BOT) | | 0.4 | | °C/W | | 9 |
| Junction-to-board thermal resistance | RθJB | | 7.6 | | °C/W | | 9 |
| Junction-to-top characterization parameter | ψJT | | 0.1 | | °C/W | | 9 |
| Junction-to-board characterization parameter | ψJB | | 7.5 | | °C/W | | 9 |
## CAD (KiCad official)
- Symbol: `DS90UB960WRTDTQ1`
- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`
- 3D model: VQFN-64(9x9) (KiCad packages3D, STEP)
- 3D model files: `ds90ub960wrtdtq1-etched.step` / `ds90ub960wrtdtq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds90ub960wrtdtq1.step` / `ds90ub960wrtdtq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds90ub960-q1) (191 pp, sha256 `60c8314e70121607`, retrieved 2026-10-28, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ds90ub960wrtdtq1-datasheet.pdf)