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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DS90UB949ATRGCTQ1

Texas Instruments · Serializers / Deserializers · VQFN-64-EP(9x9)

DS90UB949ATRGCTQ1 from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CEC	bidirectional	Consumer Electronic Control channel open-drain input/output, pulled up with a 27-kΩ resistor to 3.3 V.
2	RES0	passive	Reserved pin that must be tied to GND.
3	VDDIO	power_in	1.8-V (±5%) LVCMOS I/O supply.
4	SDIN/GPIO0	bidirectional	Master-mode I2S data input shared with bidirectional control channel GPIO0, LVCMOS level.
5	SWC/GPIO1	bidirectional	Master-mode I2S word clock output shared with bidirectional control channel GPIO1, LVCMOS level.
6	SCLK/I2CSEL	bidirectional	I2C voltage level strap sampled at power-up (tie to VDDIO with 10 kΩ for 1.8-V I2C, float for 3.3-V I2C), then operates as master-mode I2S clock output.
7	VDDL11	power_in	1.1-V (±5%) digital supply.
8	D_GPIO0/MOSI	bidirectional	High-speed control channel GPIO0 (dual-link mode only), LVCMOS, shared with SPI MOSI.
9	VDDA11	power_in	1.1-V (±5%) analog supply.
10	D_GPIO1/MISO	bidirectional	High-speed control channel GPIO1 (dual-link mode only), LVCMOS, shared with SPI MISO.
11	D_GPIO2/SPLK	bidirectional	High-speed control channel GPIO2 (dual-link mode only), LVCMOS, shared with SPI clock.
12	D_GPIO3/SS	bidirectional	High-speed control channel GPIO3 (dual-link mode only), LVCMOS, shared with SPI slave select.
13	INTB	output	Open-drain active-low interrupt output, pulled up to VDDIO with 4.7 kΩ.
14	SDA	bidirectional	I2C data open-drain input/output; requires external pullup to 1.8 V or 3.3 V per I2CSEL and must not float.
15	SCL	bidirectional	I2C clock open-drain input/output; requires external pullup to 1.8 V or 3.3 V per I2CSEL (4.7 kΩ recommended) and must not float.
16	MCLK	bidirectional	Master-mode I2S system clock input/output, LVCMOS level.
17	VDDP11	power_in	1.1-V (±5%) PLL supply.
18	MODE_SEL0	input	Analog mode select 0, configured with external resistors per the MODE_SEL resistor table.
19	IDx	input	Analog I2C serial control bus device ID address select, configured with external resistor.
20	LFT	passive	FPD-Link III analog loop filter; connect with 10-nF capacitor to GND.
21	VDDHS11	power_in	1.1-V (±5%) supply.
22	DOUT1-	output	FPD-Link III inverting output 1; AC-couple with 0.1-µF capacitor for DS90Ux92x-Q1 deserializers, or 0.1 µF or 33 nF for 94x deserializers.
23	DOUT1+	output	FPD-Link III true output 1; AC-couple with 0.1-µF capacitor for DS90Ux92x-Q1 deserializers, or 0.1 µF or 33 nF for 94x deserializers.
24	VDD18	power_in	1.8-V (±5%) analog supply.
25	VDDS11	power_in	1.1-V (±5%) serializer supply.
26	DOUT0-	output	FPD-Link III inverting output 0; AC-couple with 0.1-µF capacitor for DS90Ux92x-Q1 deserializers, or 0.1 µF or 33 nF for 94x deserializers.
27	DOUT0+	output	FPD-Link III true output 0; AC-couple with 0.1-µF capacitor for DS90Ux92x-Q1 deserializers, or 0.1 µF or 33 nF for 94x deserializers.
28	VDDHS11	power_in	1.1-V (±5%) supply.
29	RES1	passive	Reserved pin that must be tied to GND.
30	RES2	passive	Reserved pin that must be connected with 50 Ω to GND.
31	PDB	input	LVCMOS power-down mode input; PDB must be released only after all supplies are stable and is driven per the power-up sequencing limits.
32	MODE_SEL1	input	Analog mode select 1, configured with external resistors per the MODE_SEL resistor table.
33	I2S_WC/GPIO7_REG	bidirectional	Slave-mode I2S word clock input, LVCMOS, shared with register-only GPIO7.
34	I2S_CLK/GPIO8_REG	bidirectional	Slave-mode I2S clock input, LVCMOS, shared with register-only GPIO8.
35	I2S_DA/GPIO6_REG	bidirectional	Slave-mode I2S data input, LVCMOS, shared with register-only GPIO6.
36	I2S_DB/GPIO5_REG	bidirectional	Slave-mode I2S data input, LVCMOS, shared with register-only GPIO5.
37	I2S_DC/GPIO2	bidirectional	Slave-mode I2S data input, LVCMOS, shared with bidirectional control channel GPIO2.
38	I2S_DD/GPIO3	bidirectional	Slave-mode I2S data input, LVCMOS, shared with bidirectional control channel GPIO3.
39	X1	input	Optional reference clock input for CEC, requiring a 25 MHz ±0.1% (1000 ppm), 45-55% duty cycle CMOS 1.8-V clock; leave open if unused.
40	REM_INTB	output	Open-drain remote interrupt mirroring INTB_IN from the deserializer; requires external pullup to 1.8 V (4.7 kΩ recommended).
41	VDDL11	power_in	1.1-V (±5%) digital supply.
42	HPD	output	HDMI hot plug detect open-drain output, pulled up to RX_5V with 1 kΩ.
43	RX_5V	input	HDMI 5-V detect input.
44	DDC_SDA	bidirectional	DDC slave serial data open-drain input/output, pulled up to RX_5V with 47 kΩ.
45	DDC_SCL	input	DDC slave serial clock open-drain input, pulled up to RX_5V with 47 kΩ.
46	VDDIO	power_in	1.8-V (±5%) IO supply.
47	NC0	unconnected	No connect; leave floating and do not connect to VDD or GND.
48	NC1	unconnected	No connect; leave floating and do not connect to VDD or GND.
49	IN_CLK-	input	TMDS clock differential input (inverting).
50	IN_CLK+	input	TMDS clock differential input (true).
51	VDD18	power_in	1.8-V (±5%) analog supply.
52	VDDHA11	power_in	1.1-V (±5%) TMDS supply.
53	NC2	unconnected	No connect; leave floating and do not connect to VDD or GND.
54	VDDHA11	power_in	1.1-V (±5%) TMDS supply.
55	IN_D0-	input	TMDS data channel 0 differential input (inverting).
56	IN_D0+	input	TMDS data channel 0 differential input (true).
57	VTERM	power_in	3.3-V (±5%) supply for DC-coupled internal termination, or 1.8-V (±5%) supply for AC-coupled internal termination.
58	VDDHA11	power_in	1.1-V (±5%) TMDS supply.
59	IN_D1-	input	TMDS data channel 1 differential input (inverting).
60	IN_D1+	input	TMDS data channel 1 differential input (true).
61	VDDHA11	power_in	1.1-V (±5%) TMDS supply.
62	IN_D2-	input	TMDS data channel 2 differential input (inverting).
63	IN_D2+	input	TMDS data channel 2 differential input (true).
64	VDD18	power_in	1.8-V (±5%) analog supply.
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-64-EP(9x9)
Category	Communication Interface Chip/UART/485/232
Pins	65

CAD (KiCad official)

Symbol: DS90UB949ATRGCTQ1
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: ds90ub949atrgctq1-etched.step / ds90ub949atrgctq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub949atrgctq1.step / ds90ub949atrgctq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (83 pp, sha256 bac2473db01d774e, retrieved 2026-10-11, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF