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DS90UB948TNKDTQ1

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Texas Instruments Serializers / Deserializers, WQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ds90ub948tnkdtq1factory-2.0.0extractor-text
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Contents

README

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DS90UB948TNKDTQ1

Texas Instruments · Serializers / Deserializers · WQFN-64-EP(9x9)

DS90UB948TNKDTQ1 from Texas Instruments, in a WQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LOCK output Lock status output: high when the PLL has locked to the reference clock input, low when unlocked.
2 CAP_I2S passive Decoupling capacitor connection for the on-chip regulator; datasheet recommends a 0.1-µF decoupling capacitor to GND.
3 VDDIO power_in LVCMOS I/O supply, 1.8 V (±5%) or 3.3 V (±10%); requires 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
4 BISTC / INTB_IN input Multifunction pin: BIST clock select (0 = PCLK, 1 = 33 MHz) or interrupt input INTB_IN depending on register setting; weak 3-µA internal pulldown.
5 BISTEN input BIST enable: 0 disables BIST mode, 1 enables BIST mode; weak 3-µA internal pulldown, tie to pulldown if unused.
6 VDDL12_0 power_in 1.2-V (±5%) supply; requires 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND at each VDD pin.
7 SDOUT / GPIO0 / PASS bidirectional Multifunction pin: AA-mode I2S data output (SDOUT), GPIO0 (default logic LOW), or BIST PASS status output (PASS = 1 no error, 0 error detected).
8 SWC / GPIO1 bidirectional Multifunction pin: AA-mode I2S word clock output or GPIO1 (default logic LOW), with weak 3-µA internal pulldown.
9 I2S_DD / GPIO3 bidirectional Multifunction pin: SS-mode I2S data output or GPIO3 (default logic LOW), with weak 3-µA internal pulldown.
10 I2S_DC / GPIO2 bidirectional Multifunction pin: SS-mode I2S data output or GPIO2 (default logic LOW), with weak 3-µA internal pulldown.
11 I2S_DB / GPIO5_REG bidirectional Multifunction pin: SS-mode I2S data output or high-speed GPIO5 (I2C register control only, default logic LOW).
12 I2S_DA / GPIO6_REG bidirectional Multifunction pin: SS-mode I2S data output or high-speed GPIO6 (I2C register control only, default logic LOW).
13 I2S_CLK / GPIO8_REG bidirectional Multifunction pin: SS-mode I2S clock output or high-speed GPIO8 (I2C register control only, default logic LOW); disable the I2S jitter cleaner via 0x2B[7]=1 when used as I2S clock.
14 I2S_WC / GPIO7_REG bidirectional Multifunction pin: SS-mode I2S word clock output or high-speed GPIO7 (I2C register control only, default logic LOW).
15 MCLK / GPIO9 bidirectional Multifunction pin: AA-mode I2S system clock output or GPIO9 (default logic LOW), with weak 3-µA internal pulldown.
16 D_GPIO3/CS bidirectional SPI peripheral select or high-speed GPIO3 (Dual Link Mode only, default tri-state), with weak 3-µA internal pulldown.
17 D_GPIO2/SPLK bidirectional SPI clock or high-speed GPIO2 (Dual Link Mode only, default tri-state), with weak 3-µA internal pulldown.
18 D_GPIO1/POCI bidirectional SPI controller input, peripheral output, or high-speed GPIO1 (Dual Link Mode only, default tri-state), with weak 3-µA internal pulldown.
19 D_GPIO0/PICO bidirectional SPI controller output, peripheral input, or high-speed GPIO0 (Dual Link Mode only, default tri-state), with weak 3-µA internal pulldown.
20 VDD12_LVDS power_in 1.2-V (±5%) supply; requires 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
21 D7+ output OpenLDI differential data output D7+; requires external 100-Ω termination for LVDS or leave unused as no connect.
22 D7- output OpenLDI differential data output D7-; requires external 100-Ω termination for LVDS or leave unused as no connect.
23 CLK2+ output OpenLDI differential clock output CLK2+; requires external 100-Ω termination for LVDS.
24 CLK2- output OpenLDI differential clock output CLK2-; requires external 100-Ω termination for LVDS.
25 D6+ output OpenLDI differential data output D6+; requires external 100-Ω termination for LVDS.
26 D6- output OpenLDI differential data output D6-; requires external 100-Ω termination for LVDS.
27 D5+ output OpenLDI differential data output D5+; requires external 100-Ω termination for LVDS.
28 D5- output OpenLDI differential data output D5-; requires external 100-Ω termination for LVDS.
29 D4+ output OpenLDI differential data output D4+; requires external 100-Ω termination for LVDS.
30 D4- output OpenLDI differential data output D4-; requires external 100-Ω termination for LVDS.
31 VDD33_B power_in 3.3-V (±10%) supply powering the on-chip regulator; requires 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
32 VDDP12_LVDS power_in 1.2-V (±5%) supply for the LVDS output; requires 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
33 VDD25_CAP passive Decoupling capacitor connection for the on-chip regulator; datasheet recommends a 0.1-µF decoupling capacitor to GND.
34 D3+ output OpenLDI differential data output D3+; requires external 100-Ω termination for LVDS.
35 D3- output OpenLDI differential data output D3-; requires external 100-Ω termination for LVDS.
36 CLK1+ output OpenLDI differential clock output CLK1+; requires external 100-Ω termination for LVDS.
37 CLK1- output OpenLDI differential clock output CLK1-; requires external 100-Ω termination for LVDS.
38 D2+ output OpenLDI differential data output D2+; requires external 100-Ω termination for LVDS.
39 D2- output OpenLDI differential data output D2-; requires external 100-Ω termination for LVDS.
40 D1+ output OpenLDI differential data output D1+; requires external 100-Ω termination for LVDS.
41 D1- output OpenLDI differential data output D1-; requires external 100-Ω termination for LVDS.
42 D0+ output OpenLDI differential data output D0+; requires external 100-Ω termination for LVDS.
43 D0- output OpenLDI differential data output D0-; requires external 100-Ω termination for LVDS.
44 VDDL12_1 power_in 1.2-V (±5%) supply; requires 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND at each VDD pin.
45 I2C_SCL bidirectional I2C clock, open-drain; requires external pullup to VI2C (2.2 kΩ for 1.8 V or 4.7 kΩ for 3.3 V) and must not float.
46 I2C_SDA bidirectional I2C data, open-drain; requires external pullup to VI2C (2.2 kΩ for 1.8 V or 4.7 kΩ for 3.3 V) and must not float.
47 IDx input I2C serial control bus device ID address select, set with a voltage divider from a pullup to VDD33 and a pulldown to GND (Table 7-11).
48 PDB input Inverted power-down input: HIGH enables the device, LOW powers it down; default weak pulldown above 100 kΩ, and PDB should stay low until supplies reach minimum levels.
49 RES0 unconnected Reserved pin; may be left floating as no connect, or a 0.1-µF decoupling capacitor may be placed to GND.
50 MODE_SEL1 input Mode select 1 strap pin, set with a voltage divider from a pullup to VDD33 and a pulldown to GND (Table 7-9).
51 VDDP12_CH0 power_in 1.2-V (±5%) supply for channel 0; requires 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
52 VDDR12_CH0 power_in 1.2-V (±5%) supply for channel 0; requires 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
53 RIN0+ bidirectional FPD-Link III RX port 0 positive pin; must be AC-coupled per Table 8-1, and leave unused pins as no connect with no external pullup or pulldown.
54 RIN0- bidirectional FPD-Link III RX port 0 negative pin; must be AC-coupled per Table 8-1, and leave unused pins as no connect with no external pullup or pulldown.
55 CMF bidirectional Common mode filter; connect a 0.1-µF capacitor to GND.
56 VDD33_A power_in 3.3-V (±10%) supply powering the on-chip regulator; requires 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
57 VDDR12_CH1 power_in 1.2-V (±5%) supply for channel 1; requires 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
58 RIN1+ bidirectional FPD-Link III RX port 1 positive pin; must be AC-coupled per Table 8-1, and leave unused pins as no connect.
59 RIN1- bidirectional FPD-Link III RX port 1 negative pin; must be AC-coupled per Table 8-1, and leave unused pins as no connect.
60 VDDP12_CH1 power_in 1.2-V (±5%) supply for channel 1; requires 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
61 MODE_SEL0 input Mode select 0 strap pin, set with a voltage divider from a pullup to VDD33 and a pulldown to GND (Table 7-8).
62 CMLOUTP output Channel monitor loop-through driver positive output; route to a test point or pad with a 100-Ω termination between CMLOUTP and CMLOUTN.
63 CMLOUTN output Channel monitor loop-through driver negative output; route to a test point or pad with a 100-Ω termination between CMLOUTP and CMLOUTN.
64 RES1 unconnected Reserved pin; may be left floating as no connect, or a 0.1-µF decoupling capacitor may be placed to GND.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-64-EP(9x9)
Category Communication Interface Chip/UART/485/232
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD33 VDD33 -0.3 3.96 V Absolute maximum, VDD33_A and VDD33_B 11
Supply voltage VDD12 VDD12 -0.3 1.44 V Absolute maximum, VDDL, VDDP12, VDDR12, VDD12_LVDS, VDDP12_LVDS 11
VDDIO supply voltage VDDIO -0.3 3.96 V Absolute maximum 11
CML output voltage CMLOUTP, CMLOUTN -0.3 2.75 V Absolute maximum 11
FPD-Link III input voltage RIN0+, RIN0-, RIN1+, RIN1- -0.3 2.75 V Absolute maximum 11
Junction temperature TJ 150 °C Absolute maximum 11
Storage temperature range Tstg -65 150 °C Absolute maximum 11
Supply voltage VDD33 V(VDD33) 3 3.3 3.6 V 11
Supply voltage VDD12 V(VDD12) 1.14 1.2 1.26 V 11
LVCMOS I/O supply voltage 3.3 V V(VDDIO) 3 3.3 3.6 V V(VDDIO) = 3.3 V 11
LVCMOS I/O supply voltage 1.8 V V(VDDIO) 1.71 1.8 1.89 V V(VDDIO) = 1.8 V 11
Open-drain voltage V(I2C) 1.71 3.6 V I2C pins = V(I2C) 11
Operating free-air temperature TA -40 25 105 °C 11
Open LDI clock frequency (single link) 25 96 MHz Single link 11
Open LDI clock frequency (dual link) 50 192 MHz Dual link 12
Local I2C frequency fI2C 1 MHz 12
Supply noise VDD33 V(VDD33) 100 mVP-P DC to 50 MHz 12
Supply noise VDD12 V(VDD12) 25 mVP-P DC to 50 MHz 12
Junction-to-ambient thermal resistance RθJA 24.8 °C/W NKD (WQFN) 64 pins 12
Junction-to-case (bottom) thermal resistance RθJC(bot) 0.6 °C/W NKD (WQFN) 64 pins 12
Supply current normal operation VDD12 IDD12 169 223 mA PCLK = 170 MHz; 2-lane FPD-Link III input, dual-link OLDI output; VDD12 = 1.2 V 12
Supply current normal operation VDD33 IDD33 168 222 mA PCLK = 170 MHz; 2-lane FPD-Link III input, dual-link OLDI output; VDD33 = 3.6 V 12
Supply current normal operation VDDIO IDDIO 14 19 mA PCLK = 170 MHz; VDDIO = 1.89 V or 3.6 V 12
Total power consumption normal operation PT 858 1146 mW PCLK = 170 MHz; 2-lane FPD-Link III input, dual-link OLDI output 12
Total power consumption power-down mode PZ 40 70 mW PDB = 0 V 12
Supply current power-down VDD12 IDD12Z 2 30 mA PDB = 0 V; VDD12 = 1.2 V 12
Supply current power-down VDD33 IDD33Z 2 8 mA PDB = 0 V; VDD33 = 3.6 V 12
Supply current power-down VDDIO IDDIOZ 0.1 1 mA PDB = 0 V; VDDIO = 1.89 V or 3.6 V 12
High level output voltage 3.3 V LVCMOS VOH 2.4 V IOH = -4 mA 13
Low level output voltage 3.3 V LVCMOS VOL 0.4 V IOL = 4 mA 13
Low level input voltage 3.3 V LVCMOS VIL 0 0.8 V 13
High level input voltage 3.3 V LVCMOS VIH 2 V V(VDDIO) = 3.3 V 13
Input current LVCMOS IIN -10 10 µA VIN = 0 V or V(VDDIO) 13
Input capacitance LVCMOS CIN 10 pF 13
Differential threshold high voltage VTH 50 mV VCM = 2.1 V; RIN0+, RIN0-, RIN1+, RIN1- 14
Differential threshold low voltage VTL -50 mV VCM = 2.1 V 14
Input differential threshold VID 100 mV 14
Differential common-mode voltage VCM 2.1 V 14
Internal termination resistor differential RT 80 100 120 Ω 14
LVDS output voltage swing VOD setting 1 VOD 220 380 540 mVP-P RL = 100 Ω, VOD Setting 1; see Figure 6-9 14
LVDS output voltage swing VOD setting 4 VOD 530 750 970 mVP-P RL = 100 Ω, VOD Setting 4; see Figure 6-9 14
Change in VOD between complementary output states ΔVOD 1 50 mV RL = 100 Ω 14
Offset voltage VOS 1.125 1.2 1.375 V RL = 100 Ω; see Figure 6-9 14
Change in VOS between complementary output states ΔVOS 1 50 mV RL = 100 Ω 14
Output short-circuit current LVDS IOS -20 mA 14
Output tri-state LVDS driver current IOZ -500 500 µA PDB = 0 V 14
Differential output voltage loop-through monitor VOD 360 mV RL = 100 Ω; CMLOUTP, CMLOUTN 14
Differential output eye height EH 300 mV Loop-through monitor output CMLOUTP, CMLOUTN 15
Back channel bit rate Rb,BC 133 kbps Normal mode 15
Channel-to-channel skew tCCS 100 ps LVDS driver 17
Transmitter power-down delay tPDD 100 ns See Figure 6-5 17
LVDS low-to-high transition time tLVLHT 0.15 0.25 ns 20% to 80% transition, 5-pF load 17
LVDS high-to-low transition time tLVHLT 0.15 0.25 ns 80% to 20% transition, 5-pF load 17
Transmitter jitter cycle-to-cycle 2-lane dual OLDI tJCC 0.16 UI 2-lane FPD-Link III input, dual openLDI output 17
Transmitter jitter cycle-to-cycle 1-lane dual OLDI tJCC 0.04 UI 1-lane FPD-Link III input, dual openLDI output 17
SCL clock frequency fast mode fSCL 0 400 kHz Fast mode 16
SCL clock frequency fast plus mode fSCL 0 1 MHz Fast plus mode 16
Capacitive load for each bus line fast plus Cb 200 pF Fast plus mode 16
Input filter tSP tSP 50 ns Fast mode and fast plus mode 16
PDB reset low pulse tLRST 2 ms PDB 15

CAD (KiCad official)

  • Symbol: DS90UB948TNKDTQ1
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: WQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ds90ub948tnkdtq1-etched.step / ds90ub948tnkdtq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub948tnkdtq1.step / ds90ub948tnkdtq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (108 pp, sha256 ebb7858aaf88c0f6, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF