component

DS90UB940TNKDTQ1

Public Made by Adom

by adom

Texas Instruments LVDS ICs, WQFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfaceds90ub940tnkdtq1factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

DS90UB940TNKDTQ1

Texas Instruments · LVDS ICs · WQFN-64(9x9)

DS90UB940TNKDTQ1 from Texas Instruments, in a WQFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LOCK output LVCMOS lock status output: 1 means PLL acquired lock to the reference clock and DPHY outputs are active, 0 means PLL is unlocked.
2 CAP_I2S passive Decoupling capacitor connection for the on-chip regulator; requires a 0.1 µF capacitor to GND.
3 VDDIO power_in LVCMOS I/O power supply, 1.8V (±5%) or 3.3V (±10%), requires 10 µF, 1 µF, 0.1 µF and 0.01 µF capacitors to GND.
4 BISTC/INTB_IN input LVCMOS input with weak internal pull-down; BIST clock select (0: PCLK, 1: 33MHz) shared with interrupt input INTB_IN.
5 BISTEN input LVCMOS BIST enable input with weak internal pull-down; 0 disables BIST mode, 1 enables BIST mode.
6 VDDL12_0 power_in 1.2V (±5%) supply, requires 10 µF, 1 µF, 0.1 µF and 0.01 µF capacitors to GND.
7 GPIO0/SDOUT/PASS bidirectional LVCMOS BCC GPIO0 (default logic LOW), shared with master mode I2S data output SDOUT and PASS status output (1: no fault detected).
8 GPIO1/SWC bidirectional LVCMOS BCC GPIO1 (default logic LOW), shared with master mode I2S word clock output SWC.
9 I2S_DD/GPIO3 bidirectional LVCMOS BCC GPIO3 (default logic LOW), shared with slave mode I2S data output I2S_DD.
10 I2S_DC/GPIO2 bidirectional LVCMOS BCC GPIO2 (default logic LOW), shared with slave mode I2S data output I2S_DC.
11 I2S_DB/GPIO5_REG bidirectional LVCMOS general purpose I/O 5 under I2C register control only (default logic LOW), shared with slave mode I2S data output I2S_DB.
12 I2S_DA/GPIO6_REG bidirectional LVCMOS general purpose I/O 6 under I2C register control only (default logic LOW), shared with slave mode I2S data output I2S_DA.
13 I2S_CLK/GPIO8_REG bidirectional LVCMOS general purpose I/O 8 under I2C register control only (default logic LOW), shared with slave mode I2S clock output I2S_CLK.
14 I2S_WC/GPIO7_REG bidirectional LVCMOS general purpose I/O 7 under I2C register control only (default logic LOW), shared with slave mode I2S word clock output I2S_WC.
15 MCLK output LVCMOS master mode I2S system clock output, shared with GPIO9.
16 D_GPIO3/SS bidirectional LVCMOS high-speed GPIO3 for 2-lane FPD-Link III mode (default tri-state) with weak internal pull-down, shared with SPI slave select SS.
17 D_GPIO2/SPLK bidirectional LVCMOS high-speed GPIO2 for 2-lane FPD-Link III mode (default tri-state) with weak internal pull-down, shared with SPI serial clock SPLK.
18 D_GPIO1/MISO bidirectional LVCMOS high-speed GPIO1 for 2-lane FPD-Link III mode (default tri-state) with weak internal pull-down, shared with SPI Master In Slave Out.
19 D_GPIO0/MOSI bidirectional LVCMOS high-speed GPIO0 for 2-lane FPD-Link III mode (default tri-state) with weak internal pull-down, shared with SPI Master Out Slave In.
20 VDD12_CSI0 power_in 1.2V (±5%) supply, requires 10 µF, 1 µF, 0.1 µF and 0.01 µF capacitors to GND.
21 CSI0_CLK- output MIPI DPHY CSI-2 port 0 differential clock, negative; float if unused.
22 CSI0_CLK+ output MIPI DPHY CSI-2 port 0 differential clock, positive; float if unused.
23 CSI0_D0- output MIPI DPHY CSI-2 port 0 differential data pair 0, negative.
24 CSI0_D0+ output MIPI DPHY CSI-2 port 0 differential data pair 0, positive.
25 CSI0_D1- output MIPI DPHY CSI-2 port 0 differential data pair 1, negative.
26 CSI0_D1+ output MIPI DPHY CSI-2 port 0 differential data pair 1, positive.
27 CSI0_D2- output MIPI DPHY CSI-2 port 0 differential data pair 2, negative.
28 CSI0_D2+ output MIPI DPHY CSI-2 port 0 differential data pair 2, positive.
29 CSI0_D3- output MIPI DPHY CSI-2 port 0 differential data pair 3, negative.
30 CSI0_D3+ output MIPI DPHY CSI-2 port 0 differential data pair 3, positive.
31 VDD33_B power_in 3.3V (±10%) supply to on-chip regulator, requires 10 µF, 1 µF, 0.1 µF and 0.01 µF capacitors to GND; not internally connected to VDD33_A.
32 VDDP12_CSI power_in 1.2V (±5%) supply, requires 10 µF, 1 µF, 0.1 µF and 0.01 µF capacitors to GND.
33 VDD12_CSI1 power_in 1.2V (±5%) supply, requires 10 µF, 1 µF, 0.1 µF and 0.01 µF capacitors to GND.
34 CSI1_CLK- output MIPI DPHY CSI-2 port 1 differential clock, negative; float if unused.
35 CSI1_CLK+ output MIPI DPHY CSI-2 port 1 differential clock, positive; float if unused.
36 CSI1_D0- output MIPI DPHY CSI-2 port 1 differential data pair 0, negative.
37 CSI1_D0+ output MIPI DPHY CSI-2 port 1 differential data pair 0, positive.
38 CSI1_D1- output MIPI DPHY CSI-2 port 1 differential data pair 1, negative.
39 CSI1_D1+ output MIPI DPHY CSI-2 port 1 differential data pair 1, positive.
40 CSI1_D2- output MIPI DPHY CSI-2 port 1 differential data pair 2, negative.
41 CSI1_D2+ output MIPI DPHY CSI-2 port 1 differential data pair 2, positive.
42 CSI1_D3- output MIPI DPHY CSI-2 port 1 differential data pair 3, negative.
43 CSI1_D3+ output MIPI DPHY CSI-2 port 1 differential data pair 3, positive.
44 VDDL12_1 power_in 1.2V (±5%) supply, requires 10 µF, 1 µF, 0.1 µF and 0.01 µF capacitors to GND.
45 I2C_SCL bidirectional Open-drain I2C clock input/output; needs external pull-up to VDDIO (recommended 4.7 kΩ), do not float.
46 I2C_SDA bidirectional Open-drain I2C data input/output; needs external pull-up to VDDIO (recommended 4.7 kΩ), do not float.
47 IDx input Analog configuration input that sets the I2C serial control bus device ID address.
48 PDB input LVCMOS power-down input with weak internal pull-down: 1 is normal operation, 0 powers the device down; requires minimum ramp time of 200 µs.
49 CAP_PLL0 passive Decoupling capacitor connection for on-chip regulator; requires a 0.1 µF capacitor to GND.
50 MODE_SEL1 input Analog mode select 1 input; set with external pull-up to VDD33 and pull-down to GND as a voltage divider.
51 VDDP12_CH0 power_in 1.2V (±5%) supply, requires 10 µF, 1 µF, 0.1 µF and 0.01 µF capacitors to GND.
52 VDDR12_CH0 power_in 1.2V (±5%) supply, requires 10 µF, 1 µF, 0.1 µF and 0.01 µF capacitors to GND.
53 RIN0+ bidirectional FPD-Link III true CML input/output for channel 0; must be AC-coupled with a 33 nF capacitor.
54 RIN0- bidirectional FPD-Link III inverting CML input/output for channel 0; must be AC-coupled with a 33 nF capacitor.
55 CMF bidirectional CML common mode filter pin; connect a 0.1 µF capacitor to GND.
56 VDD33_A power_in 3.3V (±10%) supply to on-chip regulator, requires 10 µF, 1 µF, 0.1 µF and 0.01 µF capacitors to GND; not internally connected to VDD33_B.
57 VDDR12_CH1 power_in 1.2V (±5%) supply, requires 10 µF, 1 µF, 0.1 µF and 0.01 µF capacitors to GND.
58 RIN1+ bidirectional FPD-Link III true CML input/output for channel 1; must be AC-coupled with a 33 nF capacitor.
59 RIN1- bidirectional FPD-Link III inverting CML input/output for channel 1; must be AC-coupled with a 33 nF capacitor.
60 VDDP12_CH1 power_in 1.2V (±5%) supply, requires 10 µF, 1 µF, 0.1 µF and 0.01 µF capacitors to GND.
61 MODE_SEL0 input Analog mode select 0 input; set with external pull-up to VDD33 and pull-down to GND as a voltage divider.
62 CMLOUTP output CML monitor point (positive) for the equalized differential signal; place 0.1 µF series capacitor and 100 Ω termination.
63 CMLOUTN output CML monitor point (negative) for the equalized differential signal; place 0.1 µF series capacitor and 100 Ω termination.
64 CAP_PLL1 passive Decoupling capacitor connection for on-chip regulator; requires a 0.1 µF capacitor to GND.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-64(9x9)
Category Interface
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD33 VDD33 -0.3 4 V 9
Supply voltage VDD12 VDD12 -0.3 1.8 V 9
Supply voltage VDDIO VDDIO -0.3 4 V 9
LVCMOS I/O voltage (max = VDDIO + 0.3) -0.3 V max printed as VDDIO + 0.3 9
FPD-Link III input voltage -0.3 2.75 V 9
Junction temperature TJ 150 °C 9
Storage temperature range Tstg -65 150 °C 9
ESD HBM V(ESD) -8000 8000 V per AEC Q100-002 9
ESD CDM V(ESD) -1250 1250 V per AEC Q100-011 9
Supply Voltage VDD33 VDD33 3 3.3 3.6 V 9
Supply Voltage VDD18 VDD18 1.71 1.8 1.89 V 9
Supply Voltage VDD12 VDD12 1.14 1.2 1.26 V 9
Operating Free Air Temperature TA -40 25 105 °C 9
Pixel Clock Frequency (Single Link) 25 96 MHz 9
Pixel Clock Frequency (Dual Link) 50 170 MHz 9
Junction-to-ambient thermal resistance RθJA 24.8 °C/W WQFN (NKD) 64 pins 10
Junction-to-case (top) thermal resistance RθJC(top) 6.2 °C/W 10
Junction-to-board thermal resistance RθJB 3.6 °C/W 10
High Level Input Voltage (3.3V LVCMOS) VIH 2 V VDDIO = 3.3V ± 10%; max printed as VDDIO 10
Low Level Input Voltage (3.3V LVCMOS) VIL 0 0.8 V VDDIO = 3.3V ± 10% 10
Input Current (3.3V LVCMOS) IIN -10 10 µA VIN = 0V or VDDIO 10
High Level Output Voltage (3.3V LVCMOS) VOH 2.4 V IOH = -4mA; max printed as VDDIO 10
Low Level Output Voltage (3.3V LVCMOS) VOL 0 0.4 V IOL = +4mA 10
Output Short Circuit Current (3.3V LVCMOS) IOS -55 mA VOUT = 0V 10
Tri-state Output Current (3.3V LVCMOS) IOZ -20 20 µA PDB = 0V, VOUT = 0V or VDDIO 10
Input Capacitance (3.3V LVCMOS) CIN 10 pF 10
High Level Input Voltage (1.8V LVCMOS), min as multiple of VDDIO VIH 0.65 xVDDIO VDDIO = 1.8V ± 5%; printed 0.65 * VDDIO min, VDDIO max 10
Low Level Input Voltage (1.8V LVCMOS), max as multiple of VDDIO VIL 0.35 xVDDIO VDDIO = 1.8V ± 5%; printed 0 min, 0.35 * VDDIO max 10
Input Current (1.8V LVCMOS) IIN -10 10 µA VIN = 0V or VDDIO 10
Low Level Output Voltage (1.8V LVCMOS) VOL 0 0.45 V IOL = +4mA 10
Output Short Circuit Current (1.8V LVCMOS) IOS -35 mA VOUT = 0V 10
Tri-state Output Current (1.8V LVCMOS) IOZ -20 20 µA PDB = 0V, VOUT = 0V or VDDIO 10
Input High Level (I2C), min as multiple of VDDIO VIH 0.7 xVDDIO I2C_SDA, I2C_SCL; printed 0.7 * VDDIO min, VDD33 max 10
Input Low Level (I2C), max as multiple of VDDIO VIL 0.3 xVDDIO I2C_SDA, I2C_SCL; printed GND min, 0.3 * VDDIO max 10
Output Low Level (I2C) VOL 0 0.4 V IOL = +4mA 10
Input Current (I2C) IIN -10 10 µA VIN = 0V or VDDIO 10
Internal Termination Resistor - Differential RT 80 100 120 Ω 11
HS transmit static common-mode voltage VCMTX 150 200 250 mV 11
HS transmit differential voltage /VOD/ 140 200 270 mV 11
Single-ended output impedance ZOS 40 50 62.5 Ω 11
LPTX High Level Output Voltage VOH 1.05 1.2 1.3 V IOH = -4mA 11
LPTX Low Level Output Voltage VOL -50 50 mV IOL = +4mA 11
Total Power Consumption, Normal Operation PT 628 875 mW Checkerboard Pattern, 170MHz, 2-lane FPD-Link III Input, 2 MIPI lanes Output 11
Total Power Consumption, Power-Down Mode PZ 10 45 mW PDB = 0V 11
Supply Current IDD12, 96MHz, 2 MIPI lanes IDD12 150 250 mA VDD12 = 1.2 V, Checkerboard 96MHz, 1-lane FPD-Link III Input, 2 MIPI lanes Output 11
Supply Current IDD12, 96MHz, 4 MIPI lanes IDD12 125 225 mA VDD12 = 1.2 V, Checkerboard 96MHz, 1-lane FPD-Link III Input, 4 MIPI lanes Output 11
Supply Current IDD12, 170MHz, 2 MIPI lanes IDD12 250 345 mA VDD12 = 1.2 V, Checkerboard 170MHz, 2-lane FPD-Link III Input, 2 MIPI lanes Output 12
Supply Current IDD12, 170MHz, 4 MIPI lanes IDD12 220 300 mA VDD12 = 1.2 V, Checkerboard 170MHz, 2-lane FPD-Link III Input, 4 MIPI lanes Output 12
Supply Current IDD33 IDD33 90 122 mA VDD33 = 3.6 V 12
Supply Current IDDIO IDDIO 1 6 mA VDDIO = 1.89 V or 3.6 V 12
Supply Current IDD12Z, Power Down IDD12Z 2 30 mA PDB = 0 V, VDD12 = 1.2 V 12
Supply Current IDD33Z, Power Down IDD33Z 2 8 mA PDB = 0 V, VDD33 = 3.6 V 12
Supply Current IDDIOZ, Power Down IDDIOZ 0.1 0.3 mA PDB = 0 V, VDDIO = 1.89 V or 3.6 V 12
PDB Reset Low Pulse tLRST 2 ms PDB 13
Lock Time tDDLT 5 10 ms See Figure 4; max by characterization 13
SCL Clock Frequency, Fast Plus Mode fSCL 1 MHz Fast Plus Mode 14
HS Data bit rate, MIPI 2 Lanes HSTXDBR 350 1344 Mbps MIPI 2 Lanes 15
HS Data bit rate, MIPI 4 Lanes HSTXDBR 175 1190 Mbps MIPI 4 Lanes 15
Startup time t5 1 ms from PDB going HIGH 23

CAD (KiCad official)

  • Symbol: DS90UB940TNKDTQ1
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: WQFN-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: ds90ub940tnkdtq1-etched.step / ds90ub940tnkdtq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub940tnkdtq1.step / ds90ub940tnkdtq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (85 pp, sha256 7db79cad7ab6da57, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF