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DS90UB940NTNKDTQ1

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Texas Instruments Serializers, Deserializers, WQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS90UB940NTNKDTQ1

Texas Instruments · Serializers, Deserializers · WQFN-64-EP(9x9)

DS90UB940NTNKDTQ1 from Texas Instruments, in a WQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LOCK output Lock status output: LOCK = 1 when the PLL has locked to the reference clock and DPHY outputs are active, LOCK = 0 when the PLL is unlocked.
2 CAP_I2S passive Decoupling capacitor connection for the on-chip regulator; TI recommends a 0.1-µF decoupling capacitor to GND.
3 VDDIO power_in LVCMOS I/O power supply, 1.8 V (±5%) or 3.3 V (±10%); all single-ended data and control inputs must scale to the same VDDIO level.
4 BISTC/INTB_IN input Multifunction pin: BIST clock select (0: PCLK, 1: 33 MHz) when BIST is enabled, otherwise active-low interrupt input INTB_IN; weak 3-µA internal pulldown, tie to pulldown if unused.
5 BISTEN input BIST enable input (0: BIST disabled, 1: BIST enabled) with a weak 3-µA internal pulldown; tie to pulldown if unused.
6 VDDL12_0 power_in 1.2-V (±5%) supply; TI recommends 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND at each VDD pin.
7 SDOUT/PASS/GPIO0 bidirectional General-purpose I/O 0 (default logic LOW), shared with Master Mode I2S data output SDOUT and the PASS status output; weak 3-µA internal pulldown.
8 SWC/GPIO1 bidirectional General-purpose I/O 1 (default logic LOW), shared with Master Mode I2S word clock output SWC; weak 3-µA internal pulldown.
9 I2S_DD/GPIO3 bidirectional General-purpose I/O 3 (default logic LOW), shared with Slave Mode I2S data output I2S_DD; weak 3-µA internal pulldown.
10 I2S_DC/GPIO2 bidirectional General-purpose I/O 2 (default logic LOW), shared with Slave Mode I2S data output I2S_DC; weak 3-µA internal pulldown.
11 I2S_DB/GPIO5_REG bidirectional High-speed general-purpose I/O 5 (I2C register control only, default logic LOW), shared with Slave Mode I2S data output I2S_DB; weak 3-µA internal pulldown.
12 I2S_DA/GPIO6_REG bidirectional High-speed general-purpose I/O 6 (I2C register control only, default logic LOW), shared with Slave Mode I2S data output I2S_DA; weak 3-µA internal pulldown.
13 I2S_CLK/GPIO8_REG bidirectional High-speed general-purpose I/O 8 (I2C register control only, default logic LOW), shared with Slave Mode I2S clock output I2S_CLK; disable the I2S data jitter cleaner (0x2B[7]=1) when using this pin as I2S_CLK.
14 I2S_WC/GPIO7_REG bidirectional High-speed general-purpose I/O 7 (I2C register control only, default logic LOW), shared with Slave Mode I2S word clock output I2S_WC; weak 3-µA internal pulldown.
15 GPIO9/MCLK bidirectional General-purpose I/O 9 (default logic LOW), shared with Master Mode I2S system clock output MCLK; weak 3-µA internal pulldown.
16 D_GPIO3/SS bidirectional SPI slave select (register-programmed), shared with High-Speed GPIO 3 which is available only in Dual Link Mode and defaults to tri-state; weak 3-µA internal pulldown.
17 D_GPIO2/SPLK bidirectional SPI clock (register-programmed), shared with High-Speed GPIO 2 which is available only in Dual Link Mode and defaults to tri-state; weak 3-µA internal pulldown.
18 D_GPIO1/MISO bidirectional SPI master input / slave output (register-programmed), shared with High-Speed GPIO 1 which is available only in Dual Link Mode and defaults to tri-state; weak 3-µA internal pulldown.
19 D_GPIO0/MOSI bidirectional SPI master output / slave input (register-programmed), shared with High-Speed GPIO 0 which is available only in Dual Link Mode and defaults to tri-state; weak 3-µA internal pulldown.
20 VDD12_CSI0 power_in 1.2-V (±5%) supply for CSI-2 Port 0; 1.14 V to 1.26 V recommended operating range.
21 CSI0_CLK- output CSI-2 TX Port 0 differential clock output (negative); leave unused pins as No Connect with no pullup or pulldown.
22 CSI0_CLK+ output CSI-2 TX Port 0 differential clock output (positive); leave unused pins as No Connect with no pullup or pulldown.
23 CSI0_D0- output CSI-2 TX Port 0 differential data output 0 (negative); leave unused pins as No Connect with no pullup or pulldown.
24 CSI0_D0+ output CSI-2 TX Port 0 differential data output 0 (positive); leave unused pins as No Connect with no pullup or pulldown.
25 CSI0_D1- output CSI-2 TX Port 0 differential data output 1 (negative); leave unused pins as No Connect with no pullup or pulldown.
26 CSI0_D1+ output CSI-2 TX Port 0 differential data output 1 (positive); leave unused pins as No Connect with no pullup or pulldown.
27 CSI0_D2- output CSI-2 TX Port 0 differential data output 2 (negative); leave unused pins as No Connect with no pullup or pulldown.
28 CSI0_D2+ output CSI-2 TX Port 0 differential data output 2 (positive); leave unused pins as No Connect with no pullup or pulldown.
29 CSI0_D3- output CSI-2 TX Port 0 differential data output 3 (negative); leave unused pins as No Connect with no pullup or pulldown.
30 CSI0_D3+ output CSI-2 TX Port 0 differential data output 3 (positive); leave unused pins as No Connect with no pullup or pulldown.
31 VDD33_B power_in 3.3-V (±10%) supply to the on-chip regulator; must be externally connected, bypassed and driven to the same potential as VDD33_A because the two pins are not internally connected.
32 VDDP12_CSI power_in 1.2-V (±5%) supply for the CSI-2 output block; TI recommends 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
33 VDD12_CSI1 power_in 1.2-V (±5%) supply for CSI-2 Port 1; TI recommends 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
34 CSI1_CLK- output CSI-2 TX Port 1 differential clock output (negative); leave unused pins as No Connect with no pullup or pulldown.
35 CSI1_CLK+ output CSI-2 TX Port 1 differential clock output (positive); leave unused pins as No Connect with no pullup or pulldown.
36 CSI1_D0- output CSI-2 TX Port 1 differential data output 0 (negative); leave unused pins as No Connect with no pullup or pulldown.
37 CSI1_D0+ output CSI-2 TX Port 1 differential data output 0 (positive); leave unused pins as No Connect with no pullup or pulldown.
38 CSI1_D1- output CSI-2 TX Port 1 differential data output 1 (negative); leave unused pins as No Connect with no pullup or pulldown.
39 CSI1_D1+ output CSI-2 TX Port 1 differential data output 1 (positive); leave unused pins as No Connect with no pullup or pulldown.
40 CSI1_D2- output CSI-2 TX Port 1 differential data output 2 (negative); leave unused pins as No Connect with no pullup or pulldown.
41 CSI1_D2+ output CSI-2 TX Port 1 differential data output 2 (positive); leave unused pins as No Connect with no pullup or pulldown.
42 CSI1_D3- output CSI-2 TX Port 1 differential data output 3 (negative); leave unused pins as No Connect with no pullup or pulldown.
43 CSI1_D3+ output CSI-2 TX Port 1 differential data output 3 (positive); leave unused pins as No Connect with no pullup or pulldown.
44 VDDL12_1 power_in 1.2-V (±5%) supply; TI recommends 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND at each VDD pin.
45 I2C_SCL bidirectional Local I2C clock input/output, open-drain; TI recommends a 2.2-kΩ to 4.7-kΩ pullup to 1.8 V or 3.3 V.
46 I2C_SDA bidirectional Local I2C data input/output, open-drain; TI recommends a 2.2-kΩ to 4.7-kΩ pullup to 1.8 V or 3.3 V.
47 IDx input I2C serial control bus device ID address select strap; connect an external pullup to VDD18 and a pulldown to GND to form a voltage divider per Table 10.
48 PDB input Inverted power-down input: HIGH enables the device and resets registers to defaults, LOW powers it down with minimum power; weak 3-µA pulldown, and should remain low until supplies reach minimum levels.
49 RES0 unconnected Reserved pin; may be left as No Connect or connected to ground through a 0.1-µF capacitor.
50 MODE_SEL1 input Mode select 1 strap; connect an external pullup to VDD33 and pulldown to GND to form a voltage divider per Table 8.
51 VDDP12_CH0 power_in 1.2-V (±5%) supply for FPD-Link III channel 0; TI recommends 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
52 VDDR12_CH0 power_in 1.2-V (±5%) supply for FPD-Link III channel 0 receiver; TI recommends 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
53 RIN0+ bidirectional FPD-Link III RX Port 0 positive pin receiving forward-channel video/control and transmitting back-channel data; must be AC-coupled per Table 101.
54 RIN0- bidirectional FPD-Link III RX Port 0 negative pin receiving forward-channel video/control and transmitting back-channel data; must be AC-coupled per Table 101.
55 CMF passive Common mode filter; connect a 0.1-µF capacitor to GND.
56 VDD33_A power_in 3.3-V (±10%) supply to the on-chip regulator; must be externally connected, bypassed and driven to the same potential as VDD33_B.
57 VDDR12_CH1 power_in 1.2-V (±5%) supply for FPD-Link III channel 1 receiver; TI recommends 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
58 RIN1+ bidirectional FPD-Link III RX Port 1 positive pin receiving forward-channel video/control and transmitting back-channel data; must be AC-coupled per Table 101.
59 RIN1- bidirectional FPD-Link III RX Port 1 negative pin receiving forward-channel video/control and transmitting back-channel data; must be AC-coupled per Table 101.
60 VDDP12_CH1 power_in 1.2-V (±5%) supply for FPD-Link III channel 1; TI recommends 10-µF, 1-µF, 0.1-µF and 0.01-µF capacitors to GND.
61 MODE_SEL0 input Mode select 0 strap; connect an external pullup to VDD33 and pulldown to GND to form a voltage divider per Table 7.
62 CMLOUTP output Channel monitor loop-through driver differential output (positive); route to a test point or pad with a 100-Ω termination between the pins for channel monitoring (recommended).
63 CMLOUTN output Channel monitor loop-through driver differential output (negative); route to a test point or pad with a 100-Ω termination between the pins for channel monitoring (recommended).
64 RES1 unconnected Reserved pin; may be left as No Connect or connected to ground through a 0.1-µF capacitor.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-64-EP(9x9)
Category Interface
Pins 65

CAD (KiCad official)

  • Symbol: DS90UB940NTNKDTQ1
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: WQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ds90ub940ntnkdtq1-etched.step / ds90ub940ntnkdtq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub940ntnkdtq1.step / ds90ub940ntnkdtq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (100 pp, sha256 671ea533c2a5b5fa, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF