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DS90UB934TRGZTQ1

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Texas Instruments LVDS ICs, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Verified DS90UB934TRGZTQ1

by Ray · last 11 Nov 2026 · 1 record · files match
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11 Nov 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DS90UB934TRGZTQ1 · VQFN-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 84-page datasheet
  • ✓distributor: lcsc C2652239, digikey 296-47771-2-ND, mouser 595-DS90UB934TRGZTQ1
  • ✓family: QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-4z8w48ty/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.81)
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 59 kB, viewers/symbol.html 33 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ds90ub934trgztq1.kicad_sym✓ ds90ub934trgztq1.kicad_mod✓ ds90ub934trgztq1.step
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DS90UB934TRGZTQ1

Texas Instruments · LVDS ICs · VQFN-48-EP(7x7)

DS90UB934TRGZTQ1 from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I2C_SDA bidirectional I2C serial data for the bidirectional control bus, open-drain, with an external 2 kΩ to 4.7 kΩ pullup to VI2C recommended.
2 I2C_SCL bidirectional I2C serial clock for the bidirectional control bus, open-drain, with an external 2 kΩ to 4.7 kΩ pullup to VI2C recommended.
3 VDD11_D passive Decoupling connection for the internal digital 1.1-V regulator; requires a minimum 4.7 µF capacitor to GND and must not be connected to other 1.1-V rails.
4 OSS_SEL input Output sleep state select input with 25 kΩ internal pulldown; if unused connect to VDD, and any pullup to VDD must be ≤ 4.3 kΩ; VDDIO logic levels.
5 OEN input Output enable input with 1 MΩ internal pulldown; if unused connect to VDD, and any pullup to VDD must be ≤ 4.3 kΩ; VDDIO logic levels.
6 BISTEN input BIST enable input: high enables BIST mode, low disables it; 25 kΩ internal pulldown and VDDIO logic levels.
7 VDDIO power_in Supply for the single-ended outputs and control inputs, connectable to 1.8 V ±5% or 3 V to 3.6 V; each pin requires a minimum 10 nF capacitor to GND.
8 PCLK output Pixel clock output at VDDIO logic levels.
9 VSYNC output Vertical sync output at VDDIO logic levels.
10 HSYNC output Horizontal sync output at VDDIO logic levels.
11 ROUT11 output Parallel receive data output bit 11 at VDDIO logic levels; leave as No Connect if unused.
12 ROUT10 output Parallel receive data output bit 10 at VDDIO logic levels; leave as No Connect if unused.
13 ROUT9 output Parallel receive data output bit 9 at VDDIO logic levels; leave as No Connect if unused.
14 ROUT8 output Parallel receive data output bit 8 at VDDIO logic levels; leave as No Connect if unused.
15 ROUT7 output Parallel receive data output bit 7 at VDDIO logic levels; leave as No Connect if unused.
16 ROUT6 output Parallel receive data output bit 6 at VDDIO logic levels; leave as No Connect if unused.
17 VDD18 power_in 1.8-V ±5% power supply; requires 1 µF, 0.1 µF, and 0.01 µF capacitors to GND at each VDD pin.
18 ROUT5 output Parallel receive data output bit 5 at VDDIO logic levels; leave as No Connect if unused.
19 ROUT4 output Parallel receive data output bit 4 at VDDIO logic levels; leave as No Connect if unused.
20 VDD11_DVP passive Decoupling connection for the internal mixed-signal 1.1-V regulator; requires a minimum 4.7 µF capacitor to GND and must not be connected to other 1.1-V rails.
21 ROUT3 output Parallel receive data output bit 3 at VDDIO logic levels; leave as No Connect if unused.
22 ROUT2 output Parallel receive data output bit 2 at VDDIO logic levels; leave as No Connect if unused.
23 ROUT1 output Parallel receive data output bit 1 at VDDIO logic levels; leave as No Connect if unused.
24 ROUT0 output Parallel receive data output bit 0 at VDDIO logic levels; leave as No Connect if unused.
25 GPIO3/INTB bidirectional GPIO3 input/output that can also act as the active-low open-drain interrupt INTB; pull up with 4.7 kΩ to VI2C; unused pin may be left open or floating.
26 GPIO2 bidirectional General purpose input/output at VDDIO logic levels with a 25 kΩ typical pulldown by default; unused GPIOs can be left open or floating.
27 GPIO1 bidirectional General purpose input/output at VDDIO logic levels with a 25 kΩ typical pulldown by default; unused GPIOs can be left open or floating.
28 GPIO0 bidirectional General purpose input/output at VDDIO logic levels with a 25 kΩ typical pulldown by default; unused GPIOs can be left open or floating.
29 VDDIO power_in Supply for the single-ended outputs and control inputs, connectable to 1.8 V ±5% or 3 V to 3.6 V; each pin requires a minimum 10 nF capacitor to GND.
30 PDB input Active-high power-down input with 50 kΩ internal pulldown; the device is enabled when high and powered down when low, and the input is 3.3 V tolerant.
31 VDD18_FPD1 power_in 1.8-V ±5% high-speed transceiver (HSTRX) analog supply; requires 10 µF, 0.1 µF, and 0.01 µF capacitors to GND at each VDD pin.
32 RIN1+ bidirectional Receive input channel 1 positive FPD-Link III input and bidirectional control back-channel output; must be AC coupled, with internal 100 Ω differential termination to RIN1-.
33 RIN1- bidirectional Receive input channel 1 negative FPD-Link III input and bidirectional control back-channel output; must be AC coupled, with internal 100 Ω differential termination to RIN1+.
34 VDD11_FPD passive Decoupling connection for the internal analog 1.1-V regulator; requires a minimum 4.7 µF capacitor to GND and must not be connected to other 1.1-V rails.
35 IDX input I2C device ID strap input, set with a resistor divider between VDD18 (pin 17) and GND to select one of 8 I2C addresses (see Table 5-7).
36 VDD18_P1 power_in 1.8-V ±5% PLL supply; requires 1 µF, 0.1 µF, and 0.01 µF capacitors to GND at each VDD pin.
37 MODE input Mode select strap input, set with a resistor divider between VDD18 (pin 17) and GND to select coax/STP and RX mode (see Table 5-2).
38 CMLOUTP output Channel monitor loop-through differential output, typically left unconnected or routed to test points; terminate with a 100 Ω differential load for monitoring.
39 CMLOUTN output Channel monitor loop-through differential output, typically left unconnected or routed to test points; terminate with a 100 Ω differential load for monitoring.
40 VDD18_FPD0 power_in 1.8-V ±5% high-speed transceiver (HSTRX) analog supply; requires 10 µF, 0.1 µF, and 0.01 µF capacitors to GND at each VDD pin.
41 RIN0+ bidirectional Receive input channel 0 positive FPD-Link III input and bidirectional control back-channel output; must be AC coupled, with internal 100 Ω differential termination to RIN0-.
42 RIN0- bidirectional Receive input channel 0 negative FPD-Link III input and bidirectional control back-channel output; must be AC coupled, with internal 100 Ω differential termination to RIN0+.
43 RES passive Reserved pin with internal pull-up resistor; must be tied to GND for normal operation.
44 RES passive Reserved pin; must be left No Connect or tied to GND for normal operation.
45 VDD18_P0 power_in 1.8-V ±5% PLL supply; requires 1 µF, 0.1 µF, and 0.01 µF capacitors to GND at each VDD pin.
46 SEL input MUX select input: low selects RIN0 (channel A) and high selects RIN1 (channel B) as the active channel; 25 kΩ internal pulldown and VDDIO logic levels.
47 PASS output PASS output: high indicates error-free forward channel transmission and low indicates one or more errors in the received payload; VDDIO logic levels, leave No Connect if unused.
48 LOCK output LOCK status output: high when the PLL is locked and outputs are active, low when unlocked; VDDIO logic levels.
49 DAP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Interface
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD18 (VDD18, VDD18_P1, VDD18_P0, VDD18_FPD0, VDD18_FPD1) -0.3 2.16 V 8
Supply voltage VDDIO -0.3 3.96 V 8
FPD-Link III input voltage RIN0+, RIN0-, RIN1+, RIN1- -0.3 2.75 V Device powered up (VDD18 and VDDIO within recommended operating conditions) 8
FPD-Link III input voltage RIN0+, RIN0-, RIN1+, RIN1- (transient) -0.3 1.45 V Transient voltage; device powered down (VDD18 and VDDIO below recommended operating conditions) 8
FPD-Link III input voltage RIN0+, RIN0-, RIN1+, RIN1- (DC) -0.3 1.35 V DC voltage; device powered down (VDD18 and VDDIO below recommended operating conditions) 8
PDB voltage -0.3 3.96 V 8
Open-drain voltage GPIO3/INTB, I2C_SDA, I2C_SCL -0.3 3.96 V 8
Junction temperature 150 °C 8
Storage temperature Tstg -65 150 °C 8
Supply voltage V(VDD18) 1.71 1.8 1.89 V 9
LVCMOS supply voltage V(VDDIO) 1.71 1.8 1.89 V V(VDDIO) = 1.8 V 9
LVCMOS supply voltage V(VDDIO) 3 3.3 3.6 V V(VDDIO) = 3.3 V 9
Operating free-air temperature TA -40 25 105 °C 9
Data rate 0.7 1.87 Gbps 9
PCLK frequency 25 100 MHz 9
Local I2C frequency fI2C 1 MHz 9
Supply noise V(VDD18) V(VDD18) 50 mVP-P DC-50 MHz 9
Supply noise V(VDDIO) V(VDDIO) 50 mVP-P DC-50 MHz 9
Power-over-Coax noise RIN0+, RIN0-, RIN1+, RIN1- 20 mVP-P Measured across RIN[1:0]+ and RIN[1:0]− terminals 9
Total power consumption, normal operation PT 500 685 mW Worst case pattern; default registers; V(VDD18) = V(VDDIO) = 1.89 V; see Figure 4-5 9
Total power consumption, normal operation PT 900 1125 mW Worst case pattern; default registers; V(VDD18) = 1.89 V, V(VDDIO) = 3.6 V; see Figure 4-5 9
Deserializer supply current, VDD18 pin, 10-bit mode IDD 250 mA f = 100 MHz; worst case pattern; default registers; CL = 8 pF; V(VDD18) = 1.89 V; V(VDDIO) = 1.89 V or 3.6 V 10
Deserializer supply current, VDDIO pin, 10-bit mode IDD 60 mA f = 100 MHz; worst case pattern; default registers; CL = 8 pF; V(VDD18) = 1.89 V; V(VDDIO) = 1.89 V 10
Deserializer supply current, VDDIO pin, 10-bit mode IDD 145 mA f = 100 MHz; worst case pattern; default registers; CL = 8 pF; V(VDD18) = 1.89 V; V(VDDIO) = 3.6 V 10
Deserializer supply current, VDD18 pin, 12-bit HF mode IDD 270 mA f = 100 MHz; worst case pattern; default registers; CL = 8 pF; V(VDD18) = 1.89 V; V(VDDIO) = 1.89 V or 3.6 V 10
Deserializer supply current, VDDIO pin, 12-bit HF mode IDD 90 mA f = 100 MHz; worst case pattern; default registers; CL = 8 pF; V(VDD18) = 1.89 V; V(VDDIO) = 1.89 V 10
Deserializer supply current, VDDIO pin, 12-bit HF mode IDD 170 mA f = 100 MHz; worst case pattern; default registers; CL = 8 pF; V(VDD18) = 1.89 V; V(VDDIO) = 3.6 V 10
Deserializer supply current, VDD18 pin, 12-bit LF mode IDD 240 mA f = 50 MHz; worst case pattern; default registers; CL = 8 pF; V(VDD18) = 1.89 V; V(VDDIO) = 1.89 V or 3.6 V 10
Deserializer supply current, VDDIO pin, 12-bit LF mode IDD 80 mA f = 50 MHz; worst case pattern; default registers; CL = 8 pF; V(VDD18) = 1.89 V; V(VDDIO) = 1.89 V 10
Deserializer supply current, VDDIO pin, 12-bit LF mode IDD 155 mA f = 50 MHz; worst case pattern; default registers; CL = 8 pF; V(VDD18) = 1.89 V; V(VDDIO) = 3.6 V 10
Deserializer power-down supply current, VDD18 pin IDDZ 30 mA V(VDD18) = 1.89 V, V(VDDIO) = 3.6 V; PDB = L; all other LVCMOS inputs = 0 V; default registers 10
Deserializer power-down supply current, VDDIO pin IDDZ 10 mA V(VDD18) = 1.89 V, V(VDDIO) = 3.6 V; PDB = L; all other LVCMOS inputs = 0 V; default registers 10
Low level output voltage (1.8-V LVCMOS I/O) VOL 0.45 V IOL = 2 mA; V(VDDIO) = 1.71 V to 1.89 V 10
Output short circuit current (1.8-V LVCMOS I/O) IOS -17 mA VOUT = 0 V 10
High level output voltage (3.3-V LVCMOS I/O: GPIO[3:0], ROUT[11:0], HSYNC, VSYNC, LOCK, PASS) VOH 2.4 V IOH = -4 mA; V(VDDIO) = 3.0 V to 3.6 V 10
Low level output voltage (3.3-V LVCMOS I/O) VOL 0.4 V IOL = 4 mA; V(VDDIO) = 3.0 V to 3.6 V 10
High level input voltage (3.3-V: GPIO[3:0], OEN, SEL, OSS_SEL, BISTEN) VIH 2 V V(VDDIO) = 3.0 V to 3.6 V 10
High level input voltage (3.3-V: PDB) VIH 1.17 V 10
Low level input voltage (3.3-V: GPIO[3:0], OEN, SEL, OSS_SEL, BISTEN) VIL 0.8 V V(VDDIO) = 3.0 V to 3.6 V 11
Low level input voltage (3.3-V: PDB) VIL 0.63 V 11
Output short circuit current (3.3-V LVCMOS I/O) IOS -40 mA VOUT = 0 V 11
Output low level, I2C_SDA, I2C_SCL (standard/fast/fast-plus) VOL 0 0.4 V Standard/Fast Mode - IOL = 4 mA; Fast Plus Mode - IOL = 20 mA 11
Input hysteresis, I2C_SDA, I2C_SCL VHY 50 mV 11
Internal termination resistor, single ended (RIN) RT 40 50 60 Ω Single ended 11
Internal termination resistor, differential (RIN) RT 80 100 120 Ω Differential 11
Back channel single-ended output voltage (RIN0+, RIN1+) VOUT-BC 190 260 mV RL = 50 Ω, Coaxial configuration, forward channel disabled 11
Back channel differential output voltage (RIN0+, RIN0-, RIN1+, RIN1-) VOD-BC 380 520 mV RL = 100 Ω, STP configuration, forward channel disabled 11
Receiver output clock period, 10-bit mode (PCLK) tRCP 10 20 ns 10-bit mode; PCLK 50 - 100 MHz; see Figure 4-7 12
Receiver output clock period, 12-bit HF mode (PCLK) tRCP 10 26.7 ns 12-bit HF mode; PCLK 37.5 - 100 MHz; see Figure 4-7 12
Receiver output clock period, 12-bit LF mode (PCLK) tRCP 20 40 ns 12-bit LF mode; PCLK 25 - 50 MHz; see Figure 4-7 12
PCLK duty cycle, 10-bit mode tPDC 45 50 55 % 10-bit mode 12
PCLK duty cycle, 12-bit HF or LF mode tPDC 40 50 60 % 12-bit HF or LF mode 12
Spread spectrum clocking modulation frequency fmod 5 50 kHz SSCG[0] = ON; LVCMOS output bus; 25 - 100 MHz; see Figure 4-9 12
Single-ended input voltage (RIN) VIN 50 mV Coaxial configuration; 1010 pattern at far end of 15 m cable; measured at deserializer input pins 12
Differential input voltage (RIN) VID 100 mV STP configuration; 1010 pattern at far end of 15 m cable; measured at deserializer input pins 13
Back channel frequency (RIN0+, RIN0-, RIN1+, RIN1-) ƒBC 3.5 5.5 MHz 13
Input jitter tolerance (FPD-Link III input) TIJIT 0.4 UI 10 MHz sinusoidal jitter applied to FPD-Link III input 13
Junction-to-ambient thermal resistance (RGZ VQFN, 48 pins) RθJA 30.3 °C/W 9
Junction-to-case (top) thermal resistance (RGZ VQFN, 48 pins) RθJC(TOP) 12.3 °C/W 9
Junction-to-case (bottom) thermal resistance (RGZ VQFN, 48 pins) RθJC(BOT) 1.2 °C/W 9

CAD (KiCad official)

  • Symbol: DS90UB934TRGZTQ1
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds90ub934trgztq1-etched.step / ds90ub934trgztq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub934trgztq1.step / ds90ub934trgztq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (84 pp, sha256 2c613563cb56bb71, retrieved 2026-11-11, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF