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DS90UB934TRGZRQ1
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Texas Instruments LVDS ICs, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# DS90UB934TRGZRQ1++**Texas Instruments** · LVDS ICs · VQFN-48-EP(7x7)++DS90UB934TRGZRQ1 from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | I2C_SDA | bidirectional | I2C serial data line for bidirectional control bus communication with external 2-kΩ to 4.7-kΩ pullup resistor to VI2C recommended. |+| 2 | I2C_SCL | bidirectional | I2C serial clock line for bidirectional control bus communication with external 2-kΩ to 4.7-kΩ pullup resistor to VI2C recommended. |+| 3 | VDD11_D | passive | Decoupling capacitor connection for internal digital regulator, requires minimum 4.7-μF capacitor to GND. |+| 4 | OSS_SEL | input | Output sleep state select pin with 25-kΩ internal pulldown; if unused connect to VDD with ≤4.3-kΩ pullup resistor. |+| 5 | OEN | input | Output enable pin with 1-MΩ internal pulldown; if unused connect to VDD with ≤4.3-kΩ pullup resistor. |+| 6 | BISTEN | input | BIST enable pin with 25-kΩ internal pulldown; when HIGH enables BIST mode for at-speed testing. |+| 7 | VDDIO | power_in | VDDIO voltage supply input for single-ended outputs and control inputs, 1.8V ±5% or 3.0-3.6V with minimum 10-nF capacitor to GND. |+| 8 | PCLK | output | Pixel clock output at VDDIO logic levels, frequency range 25-100 MHz depending on mode. |+| 9 | VSYNC | output | Vertical SYNC output at VDDIO logic levels from FPD-LINK III deserializer. |+| 10 | HSYNC | output | Horizontal SYNC output at VDDIO logic levels from FPD-LINK III deserializer. |+| 11 | ROUT11 | output | Receive data output bit 11 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels. |+| 12 | ROUT10 | output | Receive data output bit 10 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels. |+| 13 | ROUT9 | output | Receive data output bit 9 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels. |+| 14 | ROUT8 | output | Receive data output bit 8 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels. |+| 15 | ROUT7 | output | Receive data output bit 7 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels. |+| 16 | ROUT6 | output | Receive data output bit 6 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels. |+| 17 | VDD18 | power_in | 1.8V ±5% power supply requiring 1-μF, 0.1-μF, and 0.01-μF capacitors to GND at each VDD pin. |+| 18 | ROUT5 | output | Receive data output bit 5 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels. |+| 19 | ROUT4 | output | Receive data output bit 4 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels. |+| 20 | VDD11_DVP | passive | Decoupling capacitor connection for internal mixed signal regulator, requires minimum 4.7-μF capacitor to GND. |+| 21 | ROUT3 | output | Receive data output bit 3 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels. |+| 22 | ROUT2 | output | Receive data output bit 2 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels. |+| 23 | ROUT1 | output | Receive data output bit 1 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels. |+| 24 | ROUT0 | output | Receive data output bit 0 of parallel CMOS interface from FPD-LINK III deserializer, configurable for 10 or 12-bit at VDDIO logic levels. |+| 25 | GPIO3/INTB | bidirectional | General purpose input/output or active-low open drain interrupt output, shared pin with pullup to VI2C required at 4.7 kΩ. |+| 26 | GPIO2 | bidirectional | General purpose input/output with 25-kΩ pulldown; unused pins may be left open or floating at VDDIO logic levels. |+| 27 | GPIO1 | bidirectional | General purpose input/output with 25-kΩ pulldown; unused pins may be left open or floating at VDDIO logic levels. |+| 28 | GPIO0 | bidirectional | General purpose input/output with 25-kΩ pulldown; unused pins may be left open or floating at VDDIO logic levels. |+| 29 | VDDIO | power_in | VDDIO voltage supply input for single-ended outputs and control inputs, 1.8V ±5% or 3.0-3.6V with minimum 10-nF capacitor to GND. |+| 30 | PDB | input | Power-down inverted input pin with 50-kΩ internal pulldown and 3.3V tolerance; HIGH enables device, LOW powers down. |+| 31 | VDD18_FPD1 | power_in | 1.8V ±5% high-speed transceiver analog power supply requiring 10-μF, 0.1-μF, and 0.01-μF capacitors to GND. |+| 32 | RIN1+ | bidirectional | Receive input channel 1 positive differential FPD-Link receiver with bidirectional control back channel and internal 100-Ω termination. |+| 33 | RIN1- | bidirectional | Receive input channel 1 negative differential FPD-Link receiver with internal 100-Ω termination to RIN1+, AC-coupled input required. |+| 34 | VDD11_FPD | passive | Decoupling capacitor connection for internal analog regulator, requires minimum 4.7-μF capacitor to GND. |+| 35 | IDX | input | I2C device ID address input via voltage divider with external pullup to VDD18 and pulldown to GND for 8 possible addresses. |+| 36 | VDD18_P1 | power_in | 1.8V ±5% PLL power supply requiring 1-μF, 0.1-μF, and 0.01-μF capacitors to GND. |+| 37 | MODE | input | Mode select configuration input via voltage divider to VDD18 and GND for selecting COAX/STP and operating mode (RAW12 HF/LF or RAW10). |+| 38 | CMLOUTP | output | Channel monitor loop-through CML driver differential output positive for observing jitter after equalization. |+| 39 | CMLOUTN | output | Channel monitor loop-through CML driver differential output negative with 100-Ω differential load termination. |+| 40 | VDD18_FPD0 | power_in | 1.8V ±5% high-speed transceiver analog power supply requiring 10-μF, 0.1-μF, and 0.01-μF capacitors to GND. |+| 41 | RIN0+ | bidirectional | Receive input channel 0 positive differential FPD-Link receiver with bidirectional control back channel and internal 100-Ω termination. |+| 42 | RIN0- | bidirectional | Receive input channel 0 negative differential FPD-Link receiver with internal 100-Ω termination to RIN0+, AC-coupled input required. |+| 43 | RES | unconnected | Reserved pin with internal pull-up resistor, must be tied to GND for normal operation. |+| 44 | RES | unconnected | Reserved pin, must be NC or tied to GND for normal operation. |+| 45 | VDD18_P0 | power_in | 1.8V ±5% PLL power supply requiring 1-μF, 0.1-μF, and 0.01-μF capacitors to GND. |+| 46 | SEL | input | MUX select digital input with 25-kΩ internal pulldown for selecting FPD Link input channel 0 or 1 at VDDIO logic levels. |+| 47 | PASS | output | PASS output HIGH for error-free transmission in forward channel, LOW indicates one or more errors detected at VDDIO logic levels. |+| 48 | LOCK | output | LOCK status output HIGH when PLL is locked and outputs active, LOW when unlocked at VDDIO logic levels. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Interface |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `DS90UB934TRGZRQ1`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `ds90ub934trgzrq1-etched.step` / `ds90ub934trgzrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds90ub934trgzrq1.step` / `ds90ub934trgzrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds90ub934-q1) (84 pp, sha256 `c545e4c689385e29`, retrieved 2026-09-22, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ds90ub934trgzrq1-datasheet.pdf)
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if unused connect to VDD with ≤4.3-kΩ pullup resistor."+ },+ {+ "number": "5",+ "name": "OEN",+ "type": "input",+ "description": "Output enable pin with 1-MΩ internal pulldown; if unused connect to VDD with ≤4.3-kΩ pullup resistor."+ },+ {+ "number": "6",+ "name": "BISTEN",+ "type": "input",+ "description": "BIST enable pin with 25-kΩ internal pulldown; when HIGH enables BIST mode for at-speed testing."+ },+ {+ "number": "7",+ "name": "VDDIO",+ "type": "power_in",+ "description": "VDDIO voltage supply input for single-ended outputs and control inputs, 1.8V ±5% or 3.0-3.6V with minimum 10-nF capacitor to GND."+ },+ {+ "number": "8",+ "name": "PCLK",+ "type": "output",+ "description": "Pixel clock output at VDDIO logic levels, frequency range 25-100 MHz depending on mode."+ },+ {+ "number": "9",+ "name": "VSYNC",+ "type": "output",+ "description": "Vertical SYNC output at VDDIO logic levels from FPD-LINK III deserializer."+ },+ {+ "number": "10",+ "name": "HSYNC",+ "type": "output",+ "description": "Horizontal SYNC output at VDDIO logic levels from FPD-LINK III deserializer."+ },+ {+ "number": "11",+ "name": "ROUT11",+ "type": "output",+ "description": "Receive data output bit 11 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."+ },+ {+ "number": "12",+ "name": "ROUT10",+ "type": "output",+ "description": "Receive data output bit 10 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."+ },+ {+ "number": "13",+ "name": "ROUT9",+ "type": "output",+ "description": "Receive data output bit 9 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."+ },+ {+ "number": "14",+ "name": "ROUT8",+ "type": "output",+ "description": "Receive data output bit 8 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."+ },+ {+ "number": "15",+ "name": "ROUT7",+ "type": "output",+ "description": "Receive data output bit 7 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."+ },+ {+ "number": "16",+ "name": "ROUT6",+ "type": "output",+ "description": "Receive data output bit 6 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."+ },+ {+ "number": "17",+ "name": "VDD18",+ "type": "power_in",+ "description": "1.8V ±5% power supply requiring 1-μF, 0.1-μF, and 0.01-μF capacitors to GND at each VDD pin."+ },+ {+ "number": "18",+ "name": "ROUT5",+ "type": "output",+ "description": "Receive data output bit 5 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."+ },+ {+ "number": "19",+ "name": "ROUT4",+ "type": "output",+ "description": "Receive data output bit 4 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."+ },+ {+ "number": "20",+ "name": "VDD11_DVP",+ "type": "passive",+ "description": "Decoupling capacitor connection for internal mixed signal regulator, requires minimum 4.7-μF capacitor to GND."+ },+ {+ "number": "21",+ "name": "ROUT3",+ "type": "output",+ "description": "Receive data output bit 3 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."+ },+ {+ "number": "22",+ "name": "ROUT2",+ "type": "output",+ "description": "Receive data output bit 2 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."+ },+ {+ "number": "23",+ "name": "ROUT1",+ "type": "output",+ "description": "Receive data output bit 1 of parallel CMOS interface, configurable for 10 or 12-bit data at VDDIO logic levels."+ },+ {+ "number": "24",+ "name": "ROUT0",+ "type": "output",+ "description": "Receive data output bit 0 of parallel CMOS interface from FPD-LINK III deserializer, configurable for 10 or 12-bit at VDDIO logic levels."+ },+ {+ "number": "25",+ "name": "GPIO3/INTB",+ "type": "bidirectional",+ "description": "General purpose input/output or active-low open drain interrupt output, shared pin with pullup to VI2C required at 4.7 kΩ."+ },+ {+ "number": "26",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General purpose input/output with 25-kΩ pulldown; unused pins may be left open or floating at VDDIO logic levels."+ },+ {+ "number": "27",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General purpose input/output with 25-kΩ pulldown; unused pins may be left open or floating at VDDIO logic levels."+ },+ {+ "number": "28",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General purpose input/output with 25-kΩ pulldown; unused pins may be left open or floating at VDDIO logic levels."+ },+ {+ "number": "29",+ "name": "VDDIO",+ "type": "power_in",+ "description": "VDDIO voltage supply input for single-ended outputs and control inputs, 1.8V ±5% or 3.0-3.6V with minimum 10-nF capacitor to GND."+ },+ {+ "number": "30",+ "name": "PDB",+ "type": "input",+ "description": "Power-down inverted input pin with 50-kΩ internal pulldown and 3.3V tolerance; HIGH enables device, LOW powers down."+ },+ {+ "number": "31",+ "name": "VDD18_FPD1",+ "type": "power_in",+ "description": "1.8V ±5% high-speed transceiver analog power supply requiring 10-μF, 0.1-μF, and 0.01-μF capacitors to GND."+ },+ {+ "number": "32",+ "name": "RIN1+",+ "type": "bidirectional",+ "description": "Receive input channel 1 positive differential FPD-Link receiver with bidirectional control back channel and internal 100-Ω termination."+ },+ {+ "number": "33",+ "name": "RIN1-",+ "type": "bidirectional",+ "description": "Receive input channel 1 negative differential FPD-Link receiver with internal 100-Ω termination to RIN1+, AC-coupled input required."+ },+ {+ "number": "34",+ "name": "VDD11_FPD",+ "type": "passive",+ "description": "Decoupling capacitor connection for internal analog regulator, requires minimum 4.7-μF capacitor to GND."+ },+ {+ "number": "35",+ "name": "IDX",+ "type": "input",+ "description": "I2C device ID address input via voltage divider with external pullup to VDD18 and pulldown to GND for 8 possible addresses."+ },+ {+ "number": "36",+ "name": "VDD18_P1",+ "type": "power_in",+ "description": "1.8V ±5% PLL power supply requiring 1-μF, 0.1-μF, and 0.01-μF capacitors to GND."+ },+ {+ "number": "37",+ "name": "MODE",+ "type": "input",+ "description": "Mode select configuration input via voltage divider to VDD18 and GND for selecting COAX/STP and operating mode (RAW12 HF/LF or RAW10)."+ },+ {+ "number": "38",+ "name": "CMLOUTP",+ "type": "output",+ "description": "Channel monitor loop-through CML driver differential output positive for observing jitter after equalization."+ },+ {+ "number": "39",+ "name": "CMLOUTN",+ "type": "output",+ "description": "Channel monitor loop-through CML driver differential output negative with 100-Ω differential load termination."+ },+ {+ "number": "40",+ "name": "VDD18_FPD0",+ "type": "power_in",+ "description": "1.8V ±5% high-speed transceiver analog power supply requiring 10-μF, 0.1-μF, and 0.01-μF capacitors to GND."+ },+ {+ "number": "41",+ "name": "RIN0+",+ "type": "bidirectional",+ "description": "Receive input channel 0 positive differential FPD-Link receiver with bidirectional control back channel and internal 100-Ω termination."+ },+ {+ "number": "42",+ "name": "RIN0-",+ "type": "bidirectional",+ "description": "Receive input channel 0 negative differential FPD-Link receiver with internal 100-Ω termination to RIN0+, AC-coupled input required."+ },+ {+ "number": "43",+ "name": "RES",+ "type": "unconnected",+ "description": "Reserved pin with internal pull-up resistor, must be tied to GND for normal operation."+ },+ {+ "number": "44",+ "name": "RES",+ "type": "unconnected",+ "description": "Reserved pin, must be NC or tied to GND for normal operation."+ },+ {+ "number": "45",+ "name": "VDD18_P0",+ "type": "power_in",+ "description": "1.8V ±5% PLL power supply requiring 1-μF, 0.1-μF, and 0.01-μF capacitors to GND."+ },+ {+ "number": "46",+ "name": "SEL",+ "type": "input",+ "description": "MUX select digital input with 25-kΩ internal pulldown for selecting FPD Link input channel 0 or 1 at VDDIO logic levels."+ },+ {+ "number": "47",+ "name": "PASS",+ "type": "output",+ "description": "PASS output HIGH for error-free transmission in forward channel, LOW indicates one or more errors detected at VDDIO logic levels."+ },+ {+ "number": "48",+ "name": "LOCK",+ "type": "output",+ "description": "LOCK status output HIGH when PLL is locked and outputs active, LOW when unlocked at VDDIO logic levels."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Thermal pad DAP located at package center and connected to GND; not a numbered pin in standard count",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 84,+ "cost_usd": 0.9193,+ "at": "2026-09-22T07:26:30"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ds90ub934-q1",+ "pages": 84,+ "sha256": "c545e4c689385e29",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}