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Contents

Pinout
Key specifications
Ordering variants
CAD (KiCad official)
Provenance

README

markdown

DS90UB929TRGCRQ1

Texas Instruments · Serializers, Deserializers · VQFN-64-EP(9x9)

DS90UB929TRGCRQ1 from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CEC	bidirectional	HDMI Consumer Electronic Control (CEC) channel input/output. Open-drain; requires an external 27 kΩ pullup to 3.3 V.
2	RES0	passive	Reserved. Tie to GND.
3	VDDIO	power_in	1.8 V (±5%) IO supply.
4	SDIN/GPIO0	bidirectional	Auxiliary I2S Master-mode data input (SDIN) shared with Bidirectional Control Channel GPIO0 (BCC GPIO0). LVCMOS.
5	SWC/GPIO1	bidirectional	Auxiliary I2S Master-mode Word Clock output (SWC) shared with BCC GPIO1. LVCMOS.
6	SCLK/I2CSEL	bidirectional	I2CSEL strap at power-up (LVCMOS input): tie to VDDIO via 10 kΩ for 1.8 V I2C, leave floating for 3.3 V I2C. After power-up the pin switches to Master-mode I2S Clock output (SCLK), shared with GPIO1 function.
7	VDDL11	power_in	1.1 V (±5%) digital supply.
8	VDDA11	power_in	1.1 V (±5%) analog supply (inferred from pinout diagram - the Pin Functions text table only lists pin 9 for VDDA11).
9	VDDA11	power_in	1.1 V (±5%) analog supply.
10	NC1	unconnected	No connect.
11	NC2	unconnected	No connect.
12	NC3	unconnected	No connect.
13	INTB	output	Local interrupt output. Open-drain, active LOW. Pull up to VDDIO with 4.7 kΩ.
14	SDA	bidirectional	I2C serial data. Open-drain; external pull-up to 1.8 V or 3.3 V required (see I2CSEL). Recommended 4.7 kΩ. Do not float.
15	SCL	bidirectional	I2C serial clock. Open-drain; external pull-up to 1.8 V or 3.3 V required (see I2CSEL). Recommended 4.7 kΩ. Do not float.
16	MCLK	bidirectional	Master-mode I2S System Clock input/output. LVCMOS.
17	VDDP11	power_in	1.1 V (±5%) PLL supply.
18	MODE_SEL0	input	Analog strap Mode Select 0. Voltage-divider setting selects device operating mode (see Table 4).
19	IDx	input	Analog strap that sets the I2C serial-control-bus device ID (address).
20	LFT	passive	FPD-Link III PLL loop filter. Connect a 10 nF capacitor to GND.
21	VDDHS11	power_in	1.1 V (±5%) supply.
22	NC4	unconnected	No connect.
23	NC5	unconnected	No connect.
24	VDD18	power_in	1.8 V (±5%) analog supply.
25	VDDS11	power_in	1.1 V (±5%) serializer supply.
26	DOUT-	output	FPD-Link III inverting differential output. AC-couple with 0.1 µF (92x deserializers) or 33 nF (94x deserializers).
27	DOUT+	output	FPD-Link III true differential output. AC-couple with 0.1 µF (92x deserializers) or 33 nF (94x deserializers).
28	VDDHS11	power_in	1.1 V (±5%) supply.
29	RES1	passive	Reserved. Tie to GND.
30	RES2	passive	Reserved. Connect with a 50 Ω resistor to GND.
31	PDB	input	Power-Down input. LVCMOS; drive LOW to place the device in power-down.
32	MODE_SEL1	input	Analog strap Mode Select 1. Voltage-divider setting selects device operating mode (see Table 4).
33	I2S_WC/GPIO7_REG	bidirectional	Slave-mode I2S Word Clock input (LVCMOS) shared with General-Purpose IO 7 (register-only control).
34	I2S_CLK/GPIO8_REG	bidirectional	Slave-mode I2S Bit Clock input (LVCMOS) shared with GPIO8 (register-only control).
35	I2S_DA/GPIO6_REG	bidirectional	Slave-mode I2S data input A (LVCMOS) shared with GPIO6 (register-only control).
36	I2S_DB/GPIO5_REG	bidirectional	Slave-mode I2S data input B (LVCMOS) shared with GPIO5 (register-only control).
37	I2S_DC/GPIO2	bidirectional	Slave-mode I2S data input C (LVCMOS) shared with BCC GPIO2.
38	I2S_DD/GPIO3	bidirectional	Slave-mode I2S data input D (LVCMOS) shared with BCC GPIO3.
39	X1	input	Optional oscillator input. 25 MHz ±0.1% (1000 ppm), 45-55% duty, CMOS-level 1.8 V reference clock used only for CEC. Leave open if unused.
40	REM_INTB	output	Remote interrupt output. Open-drain; mirrors the deserializer's INTB_IN status. Pull up to 1.8 V (recommended 4.7 kΩ). H = normal, L = interrupt request.
41	VDDL11	power_in	1.1 V (±5%) digital supply.
42	HPD	output	HDMI Hot Plug Detect output. Open-drain; pull up to RX_5V with a 1 kΩ resistor.
43	RX_5V	input	HDMI +5 V detect input from source-side +5V.
44	DDC_SDA	bidirectional	HDMI DDC slave serial data. Open-drain; pull up to RX_5V with 47 kΩ.
45	DDC_SCL	input	HDMI DDC slave serial clock. Open-drain; pull up to RX_5V with 47 kΩ.
46	VDDIO	power_in	1.8 V (±5%) IO supply.
47	NC6	unconnected	No connect.
48	NC7	unconnected	No connect.
49	IN_CLK-	input	HDMI TMDS clock differential input (negative).
50	IN_CLK+	input	HDMI TMDS clock differential input (positive).
51	VDD18	power_in	1.8 V (±5%) analog supply.
52	VDDHA11	power_in	1.1 V (±5%) TMDS supply.
53	NC8	unconnected	No connect.
54	VDDHA11	power_in	1.1 V (±5%) TMDS supply.
55	IN_D0-	input	HDMI TMDS data channel 0 differential input (negative).
56	IN_D0+	input	HDMI TMDS data channel 0 differential input (positive).
57	VTERM	power_in	HDMI TMDS input termination supply. Connect to 3.3 V (±5%) for DC-coupled input, or 1.8 V (±5%) for AC-coupled input.
58	VDDHA11	power_in	1.1 V (±5%) TMDS supply.
59	IN_D1-	input	HDMI TMDS data channel 1 differential input (negative).
60	IN_D1+	input	HDMI TMDS data channel 1 differential input (positive).
61	VDDHA11	power_in	1.1 V (±5%) TMDS supply.
62	IN_D2-	input	HDMI TMDS data channel 2 differential input (negative).
63	IN_D2+	input	HDMI TMDS data channel 2 differential input (positive).
64	VDD18	power_in	1.8 V (±5%) analog supply.
65	GND	power_in	Die-attach pad (DAP). Ground; connect to the ground plane with at least 9 vias.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-64-EP(9x9)
Category	Interface
Pins	65

Ordering variants

Same part, different packaging or reel option.

DS90UB929TRGCRQ1
DS90UB929QSQ/NOPB

CAD (KiCad official)

Symbol: DS90UB929TRGCRQ1
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: ds90ub929trgcrq1-etched.step / ds90ub929trgcrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub929trgcrq1.step / ds90ub929trgcrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (78 pp, sha256 df28ac65fe2f844f, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF