# DS90UB927QSQE

**Texas Instruments** · Serializers / Deserializers · WQFN-40-EP(6x6)

DS90UB927QSQE from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I2S_WC | input | I2S word clock and bit clock input with internal pulldown, LVCMOS levels referenced to VDDIO; shared with GPIO_REG7. |
| 2 | I2S_CLK | input | I2S bit clock input with internal pulldown, LVCMOS levels referenced to VDDIO; shared with GPIO_REG8. |
| 3 | I2S_DA | input | I2S digital audio data input with internal pulldown, LVCMOS levels referenced to VDDIO; shared with GPIO_REG6. |
| 4 | I2S_DB | input | I2S digital audio data input with internal pulldown, LVCMOS levels referenced to VDDIO; shared with GPIO_REG5. |
| 5 | I2S_DC | input | I2S digital audio data input with internal pulldown, LVCMOS levels referenced to VDDIO; shared with GPIO2. |
| 6 | I2S_DD | input | I2S digital audio data input with internal pulldown, LVCMOS levels referenced to VDDIO; shared with GPIO3. |
| 7 | VDDIO | power_in | LVCMOS I/O power, 1.8 V ±5% or 3.0 V to 3.6 V; each VDDIO pin requires a 4.7-µF capacitor to GND. |
| 8 | CAPL12 | passive | Decoupling capacitor connection for the on-chip 1.2 V regulator; requires 4.7-µF decoupling capacitor(s) to GND. |
| 9 | SCL | bidirectional | I2C clock input/output, open drain; must have an external pullup to VDD33 (recommended 4.7 kΩ) and must not float. |
| 10 | SDA | bidirectional | I2C data input/output, open drain; must have an external pullup to VDD33 (recommended 4.7 kΩ) and must not float. |
| 11 | IDx | passive | I2C address select analog input; connect to an external pullup to VDD33 and a pulldown to GND as a voltage divider, and do not float. |
| 12 | CAPP12 | passive | Decoupling capacitor connection for the on-chip 1.2 V regulator; requires 4.7-µF decoupling capacitor(s) to GND. |
| 13 | RES0 | power_in | Reserved pin; connect to GND. |
| 14 | CAPHS12 | passive | Decoupling capacitor connection for the on-chip 1.2 V regulator; requires a 4.7-µF decoupling capacitor to GND. |
| 15 | RES1 | power_in | Reserved pin; connect to GND. |
| 16 | DOUT- | output | Inverting FPD-Link III serial output; must be AC-coupled with a 0.1-µF capacitor. |
| 17 | DOUT+ | output | True FPD-Link III serial output; must be AC-coupled with a 0.1-µF capacitor. |
| 18 | PDB | input | Power-down input with internal pulldown; must be driven or pulled up to VDD33 - high enables the device, low powers it down with driver outputs HIGH and PLL shut down. |
| 19 | VDD33_A | power_in | Power to the on-chip regulator, 3.0 V to 3.6 V; must be bypassed with a 4.7-µF capacitor to GND and driven to the same potential as VDD33_B. |
| 20 | CMF | passive | Common mode filter; connect a 0.1-µF capacitor to GND (required). |
| 21 | REPEAT | input | Repeater mode select with internal pulldown; low disables repeater mode (default), high enables it, and a 10-kΩ pullup is required if set HIGH. |
| 22 | BKWD | input | Backward compatible mode select with internal pulldown; low selects DS90UH926/8Q-Q1 (default), high selects DS90UR906/8Q-Q1 or DS90UR916Q, and a 10-kΩ pullup is required if set HIGH. |
| 23 | MAPSEL | input | FPD-Link input map select with internal pulldown; low places LSBs on RxIN3± (default), high places MSBs on RxIN3±, and a 10-kΩ pullup is required if set HIGH. |
| 24 | VDDIO | power_in | LVCMOS I/O power, 1.8 V ±5% or 3.0 V to 3.6 V; each VDDIO pin requires a 4.7-µF capacitor to GND. |
| 25 | LFMODE | input | Low-frequency mode select with internal pulldown; low selects 15 MHz to 85 MHz RxCLKIN (default), high selects 5 MHz to below 15 MHz, and a 10-kΩ pullup is required if set HIGH. |
| 26 | VDD33_B | power_in | Power to the on-chip regulator, 3.0 V to 3.6 V; must be bypassed with a 4.7-µF capacitor to GND and driven to the same potential as VDD33_A. |
| 27 | INTB | output | Open-drain interrupt output; high for normal operation, low for an interrupt request, with a recommended 4.7-kΩ pullup to VDDIO that must not float. |
| 28 | CAPLVD12 | passive | Decoupling capacitor connection for the on-chip 1.2 V regulator; requires a 4.7-µF decoupling capacitor to GND. |
| 29 | RxIN0- | input | Inverting FPD-Link input data pair; requires external 100-Ω differential termination for standard LVDS levels. |
| 30 | RxIN0+ | input | True FPD-Link input data pair; requires external 100-Ω differential termination for standard LVDS levels. |
| 31 | RxIN1- | input | Inverting FPD-Link input data pair; requires external 100-Ω differential termination for standard LVDS levels. |
| 32 | RxIN1+ | input | True FPD-Link input data pair; requires external 100-Ω differential termination for standard LVDS levels. |
| 33 | RxIN2- | input | Inverting FPD-Link input data pair; requires external 100-Ω differential termination for standard LVDS levels. |
| 34 | RxIN2+ | input | True FPD-Link input data pair; requires external 100-Ω differential termination for standard LVDS levels. |
| 35 | RxCLKIN- | input | Inverting FPD-Link LVDS clock input; requires external 100-Ω differential termination for standard LVDS levels. |
| 36 | RxCLKIN+ | input | True FPD-Link LVDS clock input; requires external 100-Ω differential termination for standard LVDS levels. |
| 37 | RxIN3- | input | Inverting FPD-Link input data pair; requires external 100-Ω differential termination for standard LVDS levels. |
| 38 | RxIN3+ | input | True FPD-Link input data pair; requires external 100-Ω differential termination for standard LVDS levels. |
| 39 | GPIO0 | bidirectional | General-purpose LVCMOS I/O with internal pulldown, referenced to VDDIO. |
| 40 | GPIO1 | bidirectional | General-purpose LVCMOS I/O with internal pulldown, referenced to VDDIO. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-40-EP(6x6) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 41 |

## CAD (KiCad official)

- Symbol: `DS90UB927QSQE`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`
- 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files: `ds90ub927qsqe-etched.step` / `ds90ub927qsqe-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds90ub927qsqe.step` / `ds90ub927qsqe.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds90ub927q-q1) (59 pp, sha256 `3a7797546947a1ee`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ds90ub927qsqe-datasheet.pdf)