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DS90UB925QSQX

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Texas Instruments Interface - Specialized, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs ds90ub925qsqx: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers ds90ub925qsqx: viewers · Ray 4d ago
ds90ub925qsqx-etched.fit.json ds90ub925qsqx: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
ds90ub925qsqx-etched.glb ds90ub925qsqx: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
ds90ub925qsqx-etched.step ds90ub925qsqx: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
ds90ub925qsqx.glb Publish 0.1.0 · Ray 4d ago
ds90ub925qsqx.kicad_mod Publish 0.1.0 · Ray 4d ago
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README.md Initial commit: component/ds90ub925qsqx · Ray 4d ago

DS90UB925QSQX

Texas Instruments · Interface - Specialized · QFN-48-EP(7x7)

DS90UB925QSQX from Texas Instruments, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIN22 / B6 input LVCMOS parallel interface data input (blue bit 6) with pull-down; leave open if unused.
2 DIN23 / B7 input LVCMOS parallel interface data input (blue bit 7) with pull-down; leave open if unused.
3 HS input Horizontal sync LVCMOS input with pull-down; pulse width must be 3 PCLKs or longer when the Control Signal Filter is enabled, limited to 2 transitions per 130 PCLKs.
4 VS power_in Vertical sync LVCMOS input with pull-down; limited to 1 transition per 130 PCLKs, so minimum pulse width is 130 PCLKs.
5 DE input Data enable LVCMOS input with pull-down; pulse width must be 3 PCLKs or longer when the Control Signal Filter is enabled, limited to 2 transitions per 130 PCLKs.
6 IDx input Analog I2C device ID address select; connect to external pull-up to VDD33 and pull-down resistor forming a voltage divider, do not float.
7 CAPL12 passive Decoupling capacitor connection for on-chip regulator; requires two 4.7uF capacitors to GND.
8 SCL bidirectional I2C clock input/output, open drain; must have external pull-up to VDD33 (recommended 4.7kΩ), do not float.
9 SDA bidirectional I2C data input/output, open drain; must have external pull-up to VDD33 (recommended 4.7kΩ), do not float.
10 PCLK input Pixel clock LVCMOS input with pull-down; strobe edge set by RFB configuration register, 5 to 85 MHz.
11 I2S_DA / GPO_REG6 input I2S audio data input with pull-down, optionally usable as GPO_REG6; leave open if unused.
12 I2S_WC / GPO_REG7 input I2S audio word clock input with pull-down, optionally usable as GPO_REG7; leave open if unused.
13 I2S_CLK / GPO_REG8 input I2S audio clock input with pull-down, optionally usable as GPO_REG8; leave open if unused.
14 CAPP12 passive Decoupling capacitor connection for on-chip regulator; requires a 4.7uF capacitor to GND.
15 RES0 passive Reserved; tie to ground.
16 NC unconnected Not connected internally; do not connect.
17 CAPHS12 passive Decoupling capacitor connection for on-chip regulator; requires a 4.7uF capacitor to GND.
18 RES1 passive Reserved; tie to ground.
19 DOUT- output Inverting FPD-Link III serial output; must be AC-coupled with a 0.1µF capacitor.
20 DOUT+ output True FPD-Link III serial output; must be AC-coupled with a 0.1µF capacitor.
21 PDB input Power-down input with pull-down; H = normal operation, L = powered down with outputs HIGH, PLL shut down and registers reset.
22 VDD33 power_in Power to on-chip regulator, 3.0 V to 3.6 V; requires 4.7uF to GND.
23 CMF passive Analog common mode filter; connect 0.1µF to GND.
24 MODE_SEL input Analog device configuration select input; see Table 4.
25 DIN0 / R0 / GPIO0 bidirectional LVCMOS parallel data input with pull-down, optionally GPIO0 in 18-bit color mode; leave open if unused.
26 DIN1 / R1 / GPIO1 bidirectional LVCMOS parallel data input with pull-down, optionally GPIO1 in 18-bit color mode; leave open if unused.
27 DIN2 / R2 input LVCMOS parallel data input (red bit 2) with pull-down; leave open if unused.
28 DIN3 / R3 input LVCMOS parallel data input (red bit 3) with pull-down; leave open if unused.
29 DIN4 / R4 input LVCMOS parallel data input (red bit 4) with pull-down; leave open if unused.
30 VDDIO power_in LVCMOS I/O power, 1.8 V ±5% or 3.0 V to 3.6 V; requires 4.7uF to GND.
31 INTB output Open-drain interrupt output, H = normal, L = interrupt request; recommended 4.7kΩ pull-up to VDDIO.
32 DIN5 / R5 input LVCMOS parallel data input (red bit 5) with pull-down; leave open if unused.
33 DIN6 / R6 input LVCMOS parallel data input (red bit 6) with pull-down; leave open if unused.
34 DIN7 / R7 input LVCMOS parallel data input (red bit 7) with pull-down; leave open if unused.
35 DIN8 / G0 / GPIO2 bidirectional LVCMOS parallel data input with pull-down, optionally GPIO2 in 18-bit color mode; leave open if unused.
36 DIN9 / G1 / GPIO3 bidirectional LVCMOS parallel data input with pull-down, optionally GPIO3 in 18-bit color mode; leave open if unused.
37 DIN10 / G2 input LVCMOS parallel data input (green bit 2) with pull-down; leave open if unused.
38 DIN11 / G3 input LVCMOS parallel data input (green bit 3) with pull-down; leave open if unused.
39 DIN12 / G4 input LVCMOS parallel data input (green bit 4) with pull-down; leave open if unused.
40 DIN13 / G5 input LVCMOS parallel data input (green bit 5) with pull-down; leave open if unused.
41 DIN14 / G6 input LVCMOS parallel data input (green bit 6) with pull-down; leave open if unused.
42 DIN15 / G7 input LVCMOS parallel data input (green bit 7) with pull-down; leave open if unused.
43 DIN16 / B0 / GPO_REG4 input LVCMOS parallel data input with pull-down, optionally GPO_REG4 output set by configuration register; leave open if unused.
44 DIN17 / B1 / I2S_DB / GPO_REG5 input LVCMOS parallel data input with pull-down, usable as second-channel I2S data in 18-bit color mode or GPO_REG5; leave open if unused.
45 DIN18 / B2 input LVCMOS parallel data input (blue bit 2) with pull-down; leave open if unused.
46 DIN19 / B3 input LVCMOS parallel data input (blue bit 3) with pull-down; leave open if unused.
47 DIN20 / B4 input LVCMOS parallel data input (blue bit 4) with pull-down; leave open if unused.
48 DIN21 / B5 input LVCMOS parallel data input (blue bit 5) with pull-down; leave open if unused.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-48-EP(7x7)
Category Communication Interface Chip/UART/485/232
Pins 49

CAD (KiCad official)

  • Symbol: DS90UB925QSQX
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds90ub925qsqx-etched.step / ds90ub925qsqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub925qsqx.step / ds90ub925qsqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (53 pp, sha256 160abb2a015dc261, retrieved 2026-10-01, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF