component
DS90UB924TRHSTQ1
Public Made by Adomby adom
Texas Instruments Serializers / Deserializers, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+86@@ -0,0 +1,86 @@+# DS90UB924TRHSTQ1++**Texas Instruments** · Serializers / Deserializers · WQFN-48-EP(7x7)++DS90UB924TRHSTQ1 from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PDB | input | Power-down Mode Input Pin; must be driven or pulled up to VDD33; H=normal operation, L=powered down with tri-stated outputs and PLL shutdown. |+| 2 | CAPI2S | passive | Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND. |+| 3 | I2S_DB/GPIO_REG5 | output | I2S Data Output or General Purpose I/O Register 5 (configurable); shared functionality, requires external pulldown when GPIO configured. |+| 4 | SDA | bidirectional | I2C Data Input/Output Interface with open-drain output; must have external 4.7-kΩ pullup to VDD33, DO NOT FLOAT. |+| 5 | SCL | bidirectional | I2C Clock Input/Output Interface with open-drain output; must have external 4.7-kΩ pullup to VDD33, DO NOT FLOAT. |+| 6 | VDDIO | power_in | 1.8-V or 3.3-V LVCMOS I/O Power supply; requires 4.7-µF capacitor to GND. |+| 7 | I2S_DA/GPIO_REG6 | output | I2S Data Output or General Purpose I/O Register 6 (configurable); shared functionality. |+| 8 | I2S_CLK/GPIO_REG8 | output | I2S Bit Clock Output or General Purpose I/O Register 8 (configurable); shared functionality. |+| 9 | BISTEN | input | BIST Enable input; requires 10-kΩ pullup if set HIGH. |+| 10 | I2S_WC/GPIO_REG7 | output | I2S Word Clock Output or General Purpose I/O Register 7 (configurable); shared functionality. |+| 11 | MCLK | output | I2S Master Clock Output; drives master clock for I2S audio interface. |+| 12 | IDx | input | Analog I2C Address Select pin; external pullup to VDD33 required under all conditions, DO NOT FLOAT, connect to voltage divider. |+| 13 | GPIO1/SDOUT | bidirectional | General Purpose I/O or Auxiliary I2S Data Output; shared functionality, LVCMOS with pulldown. |+| 14 | GPIO0/SWC | bidirectional | General Purpose I/O or Auxiliary I2S Word Clock output; shared functionality, LVCMOS with pulldown. |+| 15 | TxOUT3+ | output | True LVDS Data Output for channel 3; each pair requires external 100-Ω differential termination. |+| 16 | TxOUT3- | output | Inverting LVDS Data Output for channel 3; each pair requires external 100-Ω differential termination. |+| 17 | TxCLKOUT+ | output | True LVDS Clock Output; pair requires external 100-Ω differential termination for standard LVDS levels. |+| 18 | TxCLKOUT- | output | Inverting LVDS Clock Output; pair requires external 100-Ω differential termination for standard LVDS levels. |+| 19 | TxOUT2+ | output | True LVDS Data Output for channel 2; each pair requires external 100-Ω differential termination. |+| 20 | TxOUT2- | output | Inverting LVDS Data Output for channel 2; each pair requires external 100-Ω differential termination. |+| 21 | TxOUT1+ | output | True LVDS Data Output for channel 1; each pair requires external 100-Ω differential termination. |+| 22 | TxOUT1- | output | Inverting LVDS Data Output for channel 1; each pair requires external 100-Ω differential termination. |+| 23 | TxOUT0+ | output | True LVDS Data Output for channel 0; each pair requires external 100-Ω differential termination. |+| 24 | TxOUT0- | output | Inverting LVDS Data Output for channel 0; each pair requires external 100-Ω differential termination. |+| 25 | CAPLV25 | passive | Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND. |+| 26 | MAPSEL | input | FPD-Link Output Map Select; MAPSEL=0 LSBs on TxOUT3± (default), MAPSEL=1 MSBs on TxOUT3±; requires 10-kΩ pullup if set HIGH. |+| 27 | LOCK | output | LOCK Status Output; 0=PLL unlocked with outputs idle, 1=PLL locked with active outputs; float if unused. |+| 28 | PASS | output | PASS Status Output; 0=BIST errors detected, 1=error-free transmission; float if unused. |+| 29 | CAPLV12 | passive | Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND. |+| 30 | OEN | input | Output Enable input pin; requires 10-kΩ pullup if set HIGH. |+| 31 | VDD33_B | power_in | 3.3-V power supply to on-chip regulator; requires 4.7-µF capacitor to GND. |+| 32 | LFMODE | input | Low Frequency Mode Select; LFMODE=0 (15-96 MHz, default), LFMODE=1 (5-15 MHz); requires 10-kΩ pullup if set HIGH. |+| 33 | CAPL12 | passive | Decoupling capacitor connection for on-chip regulator; requires two 4.7-µF decoupling capacitors to GND. |+| 34 | RES0 | power_in | Reserved pin; must be connected to GND. |+| 35 | OSS_SEL | input | Output Sleep State Select; requires 10-kΩ pullup if set HIGH. |+| 36 | GPIO3/I2S_DC | bidirectional | General Purpose I/O or I2S Data Output; shared functionality, LVCMOS with pulldown. |+| 37 | GPIO2/I2S_DD | bidirectional | General Purpose I/O or I2S Data Output; shared functionality, LVCMOS with pulldown. |+| 38 | VDD33_A | power_in | 3.3-V power supply to on-chip regulator; requires 4.7-µF capacitor to GND. |+| 39 | RES1 | power_in | Reserved pin; must be connected to GND. |+| 40 | RIN+ | bidirectional | FPD-Link III True Input; AC-coupled input with 0.1-µF capacitor required. |+| 41 | RIN- | bidirectional | FPD-Link III Inverting Input; AC-coupled input with 0.1-µF capacitor required. |+| 42 | CMF | passive | Analog Common Mode Filter; requires 0.1-µF capacitor to GND. |+| 43 | BISTC/INTB_IN | input | BIST Clock Select or Interrupt Input; shared functionality, LVCMOS with pulldown, requires 10-kΩ pullup if set HIGH. |+| 44 | CMLOUTP | output | True Loop-through Driver Output; monitor point for equalized forward channel differential signal. |+| 45 | CMLOUTN | output | Inverting Loop-through Driver Output; monitor point for equalized forward channel differential signal. |+| 46 | CAPR12 | passive | Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND. |+| 47 | CAPP12 | passive | Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND. |+| 48 | MODE_SEL | input | Analog Device Configuration Select; configures Backwards Compatibility, Repeater, I2S 4-channel, and Long Cable modes; connect to voltage divider, DO NOT FLOAT. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-48-EP(7x7) |+| Category | Communication Interface Chip/UART/485/232 |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `DS90UB924TRHSTQ1`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `ds90ub924trhstq1-etched.step` / `ds90ub924trhstq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds90ub924trhstq1.step` / `ds90ub924trhstq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds90ub924-q1) (64 pp, sha256 `6450a10ca9afb1ae`, retrieved 2026-10-03, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ds90ub924trhstq1-datasheet.pdf)
page.jsonadded+408@@ -0,0 +1,408 @@+{+ "slug": "ds90ub924trhstq1",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Serializers / Deserializers, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "communication interface chip-uart-485-232",+ "ds90ub924trhstq1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ds90ub924trhstq1.kicad_sym",+ "ds90ub924trhstq1.kicad_mod",+ "ds90ub924trhstq1.glb",+ "ds90ub924trhstq1.step",+ "ds90ub924trhstq1.lbr",+ "docs/hero.png",+ "docs/ds90ub924trhstq1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ds90ub924trhstq1-hero.glb",+ "ds90ub924trhstq1-hero.overlay.json"+ ],+ "component": {+ "mpn": "DS90UB924TRHSTQ1",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-48-EP(7x7)",+ "pin_count": 49,+ "category": "Communication Interface Chip/UART/485/232",+ "subcategory": "Serializers / Deserializers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ds90ub924-q1",+ "parts": {+ "symbol": "ds90ub924trhstq1.kicad_sym",+ "footprint": "ds90ub924trhstq1.kicad_mod",+ "model_3d": "ds90ub924trhstq1-hero.glb",+ "model_3d_plain": "ds90ub924trhstq1.glb",+ "model_3d_step": "ds90ub924trhstq1-etched.step",+ "model_3d_step_plain": "ds90ub924trhstq1.step",+ "lbr": "ds90ub924trhstq1.lbr"+ },+ "distributor_links": {+ "lcsc": 2652236,+ "digikey": "296-DS90UB924TRHSTQ1TR-ND",+ "mouser": "595-DS90UB924TRHSTQ1"+ },+ "distributor_check": {+ "checked_at": "2026-10-03T08:41:31Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-DS90UB924TRHSTQ1TR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DS90UB924TRHSTQ1",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "PDB",+ "type": "input",+ "description": "Power-down Mode Input Pin; must be driven or pulled up to VDD33; H=normal operation, L=powered down with tri-stated outputs and PLL shutdown."+ },+ {+ "number": "2",+ "name": "CAPI2S",+ "type": "passive",+ "description": "Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND."+ },+ {+ "number": "3",+ "name": "I2S_DB/GPIO_REG5",+ "type": "output",+ "description": "I2S Data Output or General Purpose I/O Register 5 (configurable); shared functionality, requires external pulldown when GPIO configured."+ },+ {+ "number": "4",+ "name": "SDA",+ "type": "bidirectional",+ "description": "I2C Data Input/Output Interface with open-drain output; must have external 4.7-kΩ pullup to VDD33, DO NOT FLOAT."+ },+ {+ "number": "5",+ "name": "SCL",+ "type": "bidirectional",+ "description": "I2C Clock Input/Output Interface with open-drain output; must have external 4.7-kΩ pullup to VDD33, DO NOT FLOAT."+ },+ {+ "number": "6",+ "name": "VDDIO",+ "type": "power_in",+ "description": "1.8-V or 3.3-V LVCMOS I/O Power supply; requires 4.7-µF capacitor to GND."+ },+ {+ "number": "7",+ "name": "I2S_DA/GPIO_REG6",+ "type": "output",+ "description": "I2S Data Output or General Purpose I/O Register 6 (configurable); shared functionality."+ },+ {+ "number": "8",+ "name": "I2S_CLK/GPIO_REG8",+ "type": "output",+ "description": "I2S Bit Clock Output or General Purpose I/O Register 8 (configurable); shared functionality."+ },+ {+ "number": "9",+ "name": "BISTEN",+ "type": "input",+ "description": "BIST Enable input; requires 10-kΩ pullup if set HIGH."+ },+ {+ "number": "10",+ "name": "I2S_WC/GPIO_REG7",+ "type": "output",+ "description": "I2S Word Clock Output or General Purpose I/O Register 7 (configurable); shared functionality."+ },+ {+ "number": "11",+ "name": "MCLK",+ "type": "output",+ "description": "I2S Master Clock Output; drives master clock for I2S audio interface."+ },+ {+ "number": "12",+ "name": "IDx",+ "type": "input",+ "description": "Analog I2C Address Select pin; external pullup to VDD33 required under all conditions, DO NOT FLOAT, connect to voltage divider."+ },+ {+ "number": "13",+ "name": "GPIO1/SDOUT",+ "type": "bidirectional",+ "description": "General Purpose I/O or Auxiliary I2S Data Output; shared functionality, LVCMOS with pulldown."+ },+ {+ "number": "14",+ "name": "GPIO0/SWC",+ "type": "bidirectional",+ "description": "General Purpose I/O or Auxiliary I2S Word Clock output; shared functionality, LVCMOS with pulldown."+ },+ {+ "number": "15",+ "name": "TxOUT3+",+ "type": "output",+ "description": "True LVDS Data Output for channel 3; each pair requires external 100-Ω differential termination."+ },+ {+ "number": "16",+ "name": "TxOUT3-",+ "type": "output",+ "description": "Inverting LVDS Data Output for channel 3; each pair requires external 100-Ω differential termination."+ },+ {+ "number": "17",+ "name": "TxCLKOUT+",+ "type": "output",+ "description": "True LVDS Clock Output; pair requires external 100-Ω differential termination for standard LVDS levels."+ },+ {+ "number": "18",+ "name": "TxCLKOUT-",+ "type": "output",+ "description": "Inverting LVDS Clock Output; pair requires external 100-Ω differential termination for standard LVDS levels."+ },+ {+ "number": "19",+ "name": "TxOUT2+",+ "type": "output",+ "description": "True LVDS Data Output for channel 2; each pair requires external 100-Ω differential termination."+ },+ {+ "number": "20",+ "name": "TxOUT2-",+ "type": "output",+ "description": "Inverting LVDS Data Output for channel 2; each pair requires external 100-Ω differential termination."+ },+ {+ "number": "21",+ "name": "TxOUT1+",+ "type": "output",+ "description": "True LVDS Data Output for channel 1; each pair requires external 100-Ω differential termination."+ },+ {+ "number": "22",+ "name": "TxOUT1-",+ "type": "output",+ "description": "Inverting LVDS Data Output for channel 1; each pair requires external 100-Ω differential termination."+ },+ {+ "number": "23",+ "name": "TxOUT0+",+ "type": "output",+ "description": "True LVDS Data Output for channel 0; each pair requires external 100-Ω differential termination."+ },+ {+ "number": "24",+ "name": "TxOUT0-",+ "type": "output",+ "description": "Inverting LVDS Data Output for channel 0; each pair requires external 100-Ω differential termination."+ },+ {+ "number": "25",+ "name": "CAPLV25",+ "type": "passive",+ "description": "Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND."+ },+ {+ "number": "26",+ "name": "MAPSEL",+ "type": "input",+ "description": "FPD-Link Output Map Select; MAPSEL=0 LSBs on TxOUT3± (default), MAPSEL=1 MSBs on TxOUT3±; requires 10-kΩ pullup if set HIGH."+ },+ {+ "number": "27",+ "name": "LOCK",+ "type": "output",+ "description": "LOCK Status Output; 0=PLL unlocked with outputs idle, 1=PLL locked with active outputs; float if unused."+ },+ {+ "number": "28",+ "name": "PASS",+ "type": "output",+ "description": "PASS Status Output; 0=BIST errors detected, 1=error-free transmission; float if unused."+ },+ {+ "number": "29",+ "name": "CAPLV12",+ "type": "passive",+ "description": "Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND."+ },+ {+ "number": "30",+ "name": "OEN",+ "type": "input",+ "description": "Output Enable input pin; requires 10-kΩ pullup if set HIGH."+ },+ {+ "number": "31",+ "name": "VDD33_B",+ "type": "power_in",+ "description": "3.3-V power supply to on-chip regulator; requires 4.7-µF capacitor to GND."+ },+ {+ "number": "32",+ "name": "LFMODE",+ "type": "input",+ "description": "Low Frequency Mode Select; LFMODE=0 (15-96 MHz, default), LFMODE=1 (5-15 MHz); requires 10-kΩ pullup if set HIGH."+ },+ {+ "number": "33",+ "name": "CAPL12",+ "type": "passive",+ "description": "Decoupling capacitor connection for on-chip regulator; requires two 4.7-µF decoupling capacitors to GND."+ },+ {+ "number": "34",+ "name": "RES0",+ "type": "power_in",+ "description": "Reserved pin; must be connected to GND."+ },+ {+ "number": "35",+ "name": "OSS_SEL",+ "type": "input",+ "description": "Output Sleep State Select; requires 10-kΩ pullup if set HIGH."+ },+ {+ "number": "36",+ "name": "GPIO3/I2S_DC",+ "type": "bidirectional",+ "description": "General Purpose I/O or I2S Data Output; shared functionality, LVCMOS with pulldown."+ },+ {+ "number": "37",+ "name": "GPIO2/I2S_DD",+ "type": "bidirectional",+ "description": "General Purpose I/O or I2S Data Output; shared functionality, LVCMOS with pulldown."+ },+ {+ "number": "38",+ "name": "VDD33_A",+ "type": "power_in",+ "description": "3.3-V power supply to on-chip regulator; requires 4.7-µF capacitor to GND."+ },+ {+ "number": "39",+ "name": "RES1",+ "type": "power_in",+ "description": "Reserved pin; must be connected to GND."+ },+ {+ "number": "40",+ "name": "RIN+",+ "type": "bidirectional",+ "description": "FPD-Link III True Input; AC-coupled input with 0.1-µF capacitor required."+ },+ {+ "number": "41",+ "name": "RIN-",+ "type": "bidirectional",+ "description": "FPD-Link III Inverting Input; AC-coupled input with 0.1-µF capacitor required."+ },+ {+ "number": "42",+ "name": "CMF",+ "type": "passive",+ "description": "Analog Common Mode Filter; requires 0.1-µF capacitor to GND."+ },+ {+ "number": "43",+ "name": "BISTC/INTB_IN",+ "type": "input",+ "description": "BIST Clock Select or Interrupt Input; shared functionality, LVCMOS with pulldown, requires 10-kΩ pullup if set HIGH."+ },+ {+ "number": "44",+ "name": "CMLOUTP",+ "type": "output",+ "description": "True Loop-through Driver Output; monitor point for equalized forward channel differential signal."+ },+ {+ "number": "45",+ "name": "CMLOUTN",+ "type": "output",+ "description": "Inverting Loop-through Driver Output; monitor point for equalized forward channel differential signal."+ },+ {+ "number": "46",+ "name": "CAPR12",+ "type": "passive",+ "description": "Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND."+ },+ {+ "number": "47",+ "name": "CAPP12",+ "type": "passive",+ "description": "Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND."+ },+ {+ "number": "48",+ "name": "MODE_SEL",+ "type": "input",+ "description": "Analog Device Configuration Select; configures Backwards Compatibility, Repeater, I2S 4-channel, and Long Cable modes; connect to voltage divider, DO NOT FLOAT."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pins 36-37 show conflicting assignments in TOP VIEW diagram versus Pin Functions table; table indica; Multiple pins have shared GPIO/I2S functionality that requires register configuration; verify which ; Analog configuration pins IDx and MODE_SEL require external voltage dividers to set device modes; ve",+ "exposed pad 49 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 15,+ "cost_usd": 0.2306,+ "at": "2026-10-03T08:41:01"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ds90ub924-q1",+ "pages": 64,+ "sha256": "6450a10ca9afb1ae",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}