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DS90UB924TRHSTQ1

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Texas Instruments Serializers / Deserializers, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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DS90UB924TRHSTQ1

Texas Instruments · Serializers / Deserializers · WQFN-48-EP(7x7)

DS90UB924TRHSTQ1 from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PDB input Power-down Mode Input Pin; must be driven or pulled up to VDD33; H=normal operation, L=powered down with tri-stated outputs and PLL shutdown.
2 CAPI2S passive Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND.
3 I2S_DB/GPIO_REG5 output I2S Data Output or General Purpose I/O Register 5 (configurable); shared functionality, requires external pulldown when GPIO configured.
4 SDA bidirectional I2C Data Input/Output Interface with open-drain output; must have external 4.7-kΩ pullup to VDD33, DO NOT FLOAT.
5 SCL bidirectional I2C Clock Input/Output Interface with open-drain output; must have external 4.7-kΩ pullup to VDD33, DO NOT FLOAT.
6 VDDIO power_in 1.8-V or 3.3-V LVCMOS I/O Power supply; requires 4.7-µF capacitor to GND.
7 I2S_DA/GPIO_REG6 output I2S Data Output or General Purpose I/O Register 6 (configurable); shared functionality.
8 I2S_CLK/GPIO_REG8 output I2S Bit Clock Output or General Purpose I/O Register 8 (configurable); shared functionality.
9 BISTEN input BIST Enable input; requires 10-kΩ pullup if set HIGH.
10 I2S_WC/GPIO_REG7 output I2S Word Clock Output or General Purpose I/O Register 7 (configurable); shared functionality.
11 MCLK output I2S Master Clock Output; drives master clock for I2S audio interface.
12 IDx input Analog I2C Address Select pin; external pullup to VDD33 required under all conditions, DO NOT FLOAT, connect to voltage divider.
13 GPIO1/SDOUT bidirectional General Purpose I/O or Auxiliary I2S Data Output; shared functionality, LVCMOS with pulldown.
14 GPIO0/SWC bidirectional General Purpose I/O or Auxiliary I2S Word Clock output; shared functionality, LVCMOS with pulldown.
15 TxOUT3+ output True LVDS Data Output for channel 3; each pair requires external 100-Ω differential termination.
16 TxOUT3- output Inverting LVDS Data Output for channel 3; each pair requires external 100-Ω differential termination.
17 TxCLKOUT+ output True LVDS Clock Output; pair requires external 100-Ω differential termination for standard LVDS levels.
18 TxCLKOUT- output Inverting LVDS Clock Output; pair requires external 100-Ω differential termination for standard LVDS levels.
19 TxOUT2+ output True LVDS Data Output for channel 2; each pair requires external 100-Ω differential termination.
20 TxOUT2- output Inverting LVDS Data Output for channel 2; each pair requires external 100-Ω differential termination.
21 TxOUT1+ output True LVDS Data Output for channel 1; each pair requires external 100-Ω differential termination.
22 TxOUT1- output Inverting LVDS Data Output for channel 1; each pair requires external 100-Ω differential termination.
23 TxOUT0+ output True LVDS Data Output for channel 0; each pair requires external 100-Ω differential termination.
24 TxOUT0- output Inverting LVDS Data Output for channel 0; each pair requires external 100-Ω differential termination.
25 CAPLV25 passive Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND.
26 MAPSEL input FPD-Link Output Map Select; MAPSEL=0 LSBs on TxOUT3± (default), MAPSEL=1 MSBs on TxOUT3±; requires 10-kΩ pullup if set HIGH.
27 LOCK output LOCK Status Output; 0=PLL unlocked with outputs idle, 1=PLL locked with active outputs; float if unused.
28 PASS output PASS Status Output; 0=BIST errors detected, 1=error-free transmission; float if unused.
29 CAPLV12 passive Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND.
30 OEN input Output Enable input pin; requires 10-kΩ pullup if set HIGH.
31 VDD33_B power_in 3.3-V power supply to on-chip regulator; requires 4.7-µF capacitor to GND.
32 LFMODE input Low Frequency Mode Select; LFMODE=0 (15-96 MHz, default), LFMODE=1 (5-15 MHz); requires 10-kΩ pullup if set HIGH.
33 CAPL12 passive Decoupling capacitor connection for on-chip regulator; requires two 4.7-µF decoupling capacitors to GND.
34 RES0 power_in Reserved pin; must be connected to GND.
35 OSS_SEL input Output Sleep State Select; requires 10-kΩ pullup if set HIGH.
36 GPIO3/I2S_DC bidirectional General Purpose I/O or I2S Data Output; shared functionality, LVCMOS with pulldown.
37 GPIO2/I2S_DD bidirectional General Purpose I/O or I2S Data Output; shared functionality, LVCMOS with pulldown.
38 VDD33_A power_in 3.3-V power supply to on-chip regulator; requires 4.7-µF capacitor to GND.
39 RES1 power_in Reserved pin; must be connected to GND.
40 RIN+ bidirectional FPD-Link III True Input; AC-coupled input with 0.1-µF capacitor required.
41 RIN- bidirectional FPD-Link III Inverting Input; AC-coupled input with 0.1-µF capacitor required.
42 CMF passive Analog Common Mode Filter; requires 0.1-µF capacitor to GND.
43 BISTC/INTB_IN input BIST Clock Select or Interrupt Input; shared functionality, LVCMOS with pulldown, requires 10-kΩ pullup if set HIGH.
44 CMLOUTP output True Loop-through Driver Output; monitor point for equalized forward channel differential signal.
45 CMLOUTN output Inverting Loop-through Driver Output; monitor point for equalized forward channel differential signal.
46 CAPR12 passive Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND.
47 CAPP12 passive Decoupling capacitor connection for on-chip regulator; requires 4.7-µF capacitor to GND.
48 MODE_SEL input Analog Device Configuration Select; configures Backwards Compatibility, Repeater, I2S 4-channel, and Long Cable modes; connect to voltage divider, DO NOT FLOAT.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48-EP(7x7)
Category Communication Interface Chip/UART/485/232
Pins 49

CAD (KiCad official)

  • Symbol: DS90UB924TRHSTQ1
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds90ub924trhstq1-etched.step / ds90ub924trhstq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub924trhstq1.step / ds90ub924trhstq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (64 pp, sha256 6450a10ca9afb1ae, retrieved 2026-10-03, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF