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DS90UB914QSQX

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Texas Instruments Serializers, Deserializers, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS90UB914QSQX

Texas Instruments · Serializers, Deserializers · WQFN-48-EP(7x7)

DS90UB914QSQX from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SDA bidirectional Open-drain data line for the I2C-compatible bidirectional control bus; requires an external pullup resistor to VDDIO.
2 SCL bidirectional Open-drain clock line for the I2C-compatible bidirectional control bus; requires an external pullup resistor to VDDIO.
3 VDDSSCG power_in SSCG PLL analog power, 1.8 V ±5%.
4 OSS_SEL input LVCMOS output sleep state select input with pulldown; works with OEN to set output states per Table 5.
5 OEN input LVCMOS output enable input with pulldown; see Table 5 for output states.
6 BISTEN input BIST enable input with pulldown; H enables BIST mode, L disables it.
7 VDDIO3 power_in LVCMOS I/O buffer power for outputs and control inputs, 1.8 V ±5% or 3.3 V ±10%.
8 PCLK output LVCMOS pixel clock output; strobe edge set by the RRFB control register.
9 VSYNC output LVCMOS vertical SYNC output.
10 HSYNC output LVCMOS horizontal SYNC output.
11 ROUT[11] output LVCMOS parallel data output bit 11.
12 ROUT[10] output LVCMOS parallel data output bit 10.
13 ROUT[9] output LVCMOS parallel data output bit 9.
14 ROUT[8] output LVCMOS parallel data output bit 8.
15 ROUT[7] output LVCMOS parallel data output bit 7.
16 ROUT[6] output LVCMOS parallel data output bit 6.
17 VDDD power_in Digital core power, 1.8 V ±5%.
18 ROUT[5] output LVCMOS parallel data output bit 5.
19 ROUT[4] output LVCMOS parallel data output bit 4.
20 VDDIO2 power_in LVCMOS I/O buffer power for outputs and control inputs, 1.8 V ±5% or 3.3 V ±10%.
21 ROUT[3] output LVCMOS parallel data output bit 3.
22 ROUT[2] output LVCMOS parallel data output bit 2.
23 ROUT[1] output LVCMOS parallel data output bit 1.
24 ROUT[0] output LVCMOS parallel data output bit 0.
25 GPIO[3] bidirectional LVCMOS general-purpose I/O that can be input for serializer GPO3 or output following local register; output-only with an external oscillator.
26 GPIO[2] bidirectional LVCMOS general-purpose I/O that can be input for serializer GPO2 or output following local register; output-only with an external oscillator.
27 GPIO[1] bidirectional LVCMOS general-purpose I/O that can be input for the corresponding serializer GPO or output following local register settings.
28 GPIO[0] bidirectional LVCMOS general-purpose I/O that can be input for the corresponding serializer GPO or output following local register settings.
29 VDDIO1 power_in LVCMOS I/O buffer power for outputs and control inputs, 1.8 V ±5% or 3.3 V ±10%.
30 PDB input Power-down input with pulldown; H enables the deserializer, L puts it in sleep and register data are not retained.
31 VDDCML1 power_in CML and bidirectional control channel driver power, 1.8 V ±5%.
32 RIN1+ bidirectional Noninverting CML differential input and bidirectional control channel; must be AC coupled with a 100-nF capacitor.
33 RIN1- bidirectional Inverting CML differential input and bidirectional control channel; must be AC coupled with a 100-nF capacitor.
34 IDx[1] input Analog I2C device address select input, set by a resistor to ground with a 10-kΩ pullup to the 1.8-V rail.
35 IDx[0] input Analog I2C device address select input, set by a resistor to ground with a 10-kΩ pullup to the 1.8-V rail.
36 VDDR power_in RX analog power, 1.8 V ±5%.
37 MODE input Mode select input with pullup; resistor to ground and 10-kΩ pullup to 1.8 V selects 12-bit low-frequency (10-50 MHz), 12-bit high-frequency (15-75 MHz) or 10-bit (20-100 MHz) mode.
38 CMLOUTP output CML test output; route to a test point or leave open if unused.
39 CMLOUTN output CML test output; route to a test point or leave open if unused.
40 VDDCML0 power_in CML and bidirectional control channel driver power, 1.8 V ±5%.
41 RIN0+ bidirectional Noninverting CML differential input and bidirectional control channel; must be AC coupled with a 100-nF capacitor.
42 RIN0- bidirectional Inverting CML differential input and bidirectional control channel; must be AC coupled with a 100-nF capacitor.
43 RES input Reserved; this pin must always be tied low.
44 RES input Reserved; this pin must always be tied low.
45 VDDPLL power_in PLL analog power, 1.8 V ±5%.
46 SEL input MUX select input with pulldown; L selects RIN0± (input A), H selects RIN1± (input B) as the active channel.
47 PASS output BIST pass output; H means error-free transmission, L means one or more errors detected; leave open if unused.
48 LOCK output Lock status output; H means PLL locked and outputs active, L means unlocked with output states set by OSS_SEL.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48-EP(7x7)
Category Interface
Pins 49

CAD (KiCad official)

  • Symbol: DS90UB914QSQX
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds90ub914qsqx-etched.step / ds90ub914qsqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub914qsqx.step / ds90ub914qsqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (74 pp, sha256 17f29c7167b0a48e, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF