component

DS90UB635TRHBRQ1

Public Made by Adom

by adom

Texas Instruments Serializers, Deserializers, QFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfaceds90ub635trhbrq1factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

DS90UB635TRHBRQ1

Texas Instruments · Serializers, Deserializers · QFN-32(5x5)

DS90UB635TRHBRQ1 from Texas Instruments, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CSI_D1P input DPHY CSI-2 data input; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnect, and it may be left floating if unused.
2 CSI_D1N input DPHY CSI-2 data input; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnect, and it may be left floating if unused.
3 CSI_D0P input DPHY CSI-2 data input; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnect, and it may be left floating if unused.
4 CSI_D0N input DPHY CSI-2 data input; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnect, and it may be left floating if unused.
5 CSI_CLKP input DPHY CSI-2 clock input; connect to a CSI-2 clock source with matched 100-Ω (±5%) impedance interconnect.
6 CSI_CLKN input DPHY CSI-2 clock input; connect to a CSI-2 clock source with matched 100-Ω (±5%) impedance interconnect.
7 RES0 input Reserved pin; connect to GND.
8 PDB input Power-down inverted input with internal 1-MΩ pulldown; PDB = 1.8 V enables the device and PDB = 0 powers it down, and the PDB input is not 3.3-V tolerant.
9 LPF1 passive Loop filter 1; connect a 0.022-µF capacitor to VDDPLL (pin 11) with the loop kept as small as possible.
10 VDDPLL_CAP passive Internal analog regulator output for decoupling; typically 10-µF, 0.1-µF, and 0.01-µF capacitors to GND, and must not be connected to an external supply rail.
11 VDDPLL power_in 1.8-V (±5%) analog power supply pin; typically bypassed with 1-µF and 0.01-µF capacitors to GND.
12 LPF2 passive Loop filter 2; connect a 0.1-µF capacitor from this pin to GND.
13 DOUT- bidirectional FPD-Link III input/output pin that must be AC-coupled; the FPD-Link III output voltage is limited to -0.3 V to 1.21 V.
14 DOUT+ bidirectional FPD-Link III input/output pin that must be AC-coupled; the FPD-Link III output voltage is limited to -0.3 V to 1.21 V.
15 VDDDRV_CAP passive Internal analog regulator output for decoupling; typically 10-µF, 0.1-µF, and 0.01-µF capacitors to GND, and must not be connected to an external supply rail.
16 VDDDRV power_in 1.8-V (±5%) analog power supply pin; typically bypassed with 1-µF and 0.01-µF capacitors to GND.
17 GPIO_0 bidirectional General-purpose input/output that defaults to an input with a 300-kΩ (typical) internal pulldown at power-up; may be left floating, but TI recommends setting GPIOx_INPUT_EN to 0 to disable it.
18 GPIO_1 bidirectional General-purpose input/output that defaults to an input with a 300-kΩ (typical) internal pulldown at power-up; may be left floating, but TI recommends setting GPIOx_INPUT_EN to 0 to disable it.
19 CLK_OUT/IDX bidirectional IDX strap input sets the I2C pull-up voltage and device address when PDB goes HIGH and then becomes CLK_OUT; if CLK_OUT is used the minimum resistance on the pin is 35 kΩ, and if unused it may be tied to GND.
20 CLKIN input Reference clock input; connect to a local clock source in non-sync external clock mode, and it may be left open in other clocking modes.
21 MODE input Mode-select strap input sampled when PDB transitions LOW to HIGH to set the default operating mode, typically set with a voltage divider between VDD18 and GND.
22 RES1 unconnected Reserved pin; do not connect (leave floating).
23 I2C_SDA bidirectional Open-drain I2C data pin, typically pulled up by 470-Ω to 4.7-kΩ resistors to a 1.8-V or 3.3-V rail depending on the IDX setting; absolute maximum open-drain voltage is -0.3 V to 3.96 V.
24 I2C_SCL bidirectional Open-drain I2C clock pin, typically pulled up by 470-Ω to 4.7-kΩ resistors to a 1.8-V or 3.3-V rail depending on the IDX setting; absolute maximum open-drain voltage is -0.3 V to 3.96 V.
25 VDDD power_in 1.8-V (±5%) power supply pin; typically bypassed with 1-µF and 0.01-µF capacitors to GND.
26 VDDD_CAP passive Internal analog regulator output for decoupling; typically 10-µF, 0.1-µF, and 0.01-µF capacitors to GND, and must not be connected to an external supply rail.
27 GPIO_2 bidirectional General-purpose input/output that defaults to an input with a 300-kΩ (typical) internal pulldown at power-up; may be left floating, but TI recommends setting GPIOx_INPUT_EN to 0 to disable it.
28 GPIO_3 bidirectional General-purpose input/output that defaults to an input with a 300-kΩ (typical) internal pulldown at power-up; may be left floating, but TI recommends setting GPIOx_INPUT_EN to 0 to disable it.
29 CSI_D3P input DPHY CSI-2 data input; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnect, and it may be left floating if unused.
30 CSI_D3N input DPHY CSI-2 data input; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnect, and it may be left floating if unused.
31 CSI_D2P input DPHY CSI-2 data input; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnect, and it may be left floating if unused.
32 CSI_D2N input DPHY CSI-2 data input; connect to a CSI-2 data source with matched 100-Ω (±5%) impedance interconnect, and it may be left floating if unused.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-32(5x5)
Category Interface
Pins 33

CAD (KiCad official)

  • Symbol: DS90UB635TRHBRQ1
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: ds90ub635trhbrq1-etched.step / ds90ub635trhbrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub635trhbrq1.step / ds90ub635trhbrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (83 pp, sha256 504de8fca9d823ef, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF