component

DS90UB633ARTVRQ1

Public Made by Adom

by adom

Texas Instruments Serializers, Deserializers, WQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfaceds90ub633artvrq1factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7h ago
viewers ds90ub633artvrq1: viewers · Ray 7h ago
ds90ub633artvrq1-etched.glb ds90ub633artvrq1: factory component page (tier=lcsc) · Ray 7h ago
ds90ub633artvrq1-etched.step ds90ub633artvrq1: factory component page (tier=lcsc) · Ray 7h ago
ds90ub633artvrq1-hero.glb ds90ub633artvrq1: hero GLB from the etched model (keeps the MPN mark) · Ray 6h ago
ds90ub633artvrq1-hero.overlay.json Publish 0.1.0 · Ray 7h ago
ds90ub633artvrq1.glb Publish 0.1.0 · Ray 7h ago
ds90ub633artvrq1.kicad_mod Publish 0.1.0 · Ray 7h ago
ds90ub633artvrq1.kicad_sym Publish 0.1.0 · Ray 7h ago
ds90ub633artvrq1.lbr Publish 0.1.0 · Ray 7h ago
ds90ub633artvrq1.step Publish 0.1.0 · Ray 7h ago
package.json Publish 0.1.0 · Ray 7h ago
page.json Set visibility: public · Ray 7h ago
README.md Initial commit: component/ds90ub633artvrq1 · Ray 7h ago

DS90UB633ARTVRQ1

Texas Instruments · Serializers, Deserializers · WQFN-32(5x5)

DS90UB633ARTVRQ1 from Texas Instruments, in a WQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 HSYNC input Horizontal sync input with LVCMOS levels and internal pulldown; in 10-bit mode HS is restricted to no more than one transition per 10 PCLK cycles, and it may be left open if unused.
2 VSYNC input Vertical sync input with LVCMOS levels and internal pulldown; in 10-bit mode VS is restricted to no more than one transition per 10 PCLK cycles, and it may be left open if unused.
3 PCLK input Pixel clock input with LVCMOS levels and internal pulldown; the data strobe edge is set by register 0x03[0] (TRFB).
4 SCL bidirectional Clock line of the I2C-compatible bidirectional control bus, open-drain, requiring an external pullup resistor to V(VDDIO).
5 SDA bidirectional Data line of the I2C-compatible bidirectional control bus, open-drain, requiring an external pullup resistor to V(VDDIO).
6 IDX input Analog device ID address select; a resistor (RID) to ground and a 10-kΩ pullup to the 1.8 V rail set the serializer I2C device address per table 7-6.
7 RES input Reserved pin with LVCMOS levels and internal pulldown that MUST be tied LOW.
8 MODE input Analog device mode select; a resistor to ground and a 10-kΩ pullup to the 1.8 V rail select PCLK-from-imager or external-oscillator operation per table 7-2.
9 PDB input Power-down input with LVCMOS levels and internal pulldown; PDB = H enables the serializer, and PDB = L puts it in power-down with the PLL shut down and control register data not retained.
10 VDDPLL power_in Analog PLL power supply, 1.8 V ±5%.
11 VDDT power_in Analog Tx analog power supply, 1.8 V ±5%.
12 DOUT- bidirectional Inverting CML differential output and bidirectional control channel input; the interconnect must be AC-coupled with a 0.1-µF capacitor (0.047-µF in series with 50 Ω for single-ended coax).
13 DOUT+ bidirectional Non-inverting CML differential output and bidirectional control channel input; the interconnect must be AC-coupled with a 0.1-µF capacitor.
14 VDDCML power_in Analog CML and bidirectional channel driver power supply, 1.8 V ±5%.
15 GPO[0] output General-purpose LVCMOS output that follows GPIO[0] from the deserializer or the local serializer register; leave open if unused.
16 GPO[1] output General-purpose LVCMOS output that follows GPIO[1] from the deserializer or the local serializer register; leave open if unused.
17 GPO[2]/CLKOUT output General-purpose LVCMOS output (GPIO[2] or local register) that also serves as the divided-clock output in external oscillator mode; it is recommended to pull it to GND with at least 40 kΩ to ensure LOW when PDB rises.
18 GPO[3]/CLKIN bidirectional General-purpose LVCMOS input/output (GPIO[3] or local register) that serves as the external oscillator clock input in external oscillator mode; leave open if unused.
19 DIN[0] input Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect.
20 DIN[1] input Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect.
21 DIN[2] input Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect.
22 DIN[3] input Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect.
23 DIN[4] input Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect.
24 DIN[5] input Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect.
25 VDDIO power_in I/O stage power supply for the single-ended inputs, SDA and SCL; may be 1.8 V ±5%, 2.8 V ±10%, or 3.3 V ±10%.
26 DIN[6] input Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect.
27 DIN[7] input Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect.
28 VDDD power_in Digital core power supply, 1.8 V ±5%.
29 DIN[8] input Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect.
30 DIN[9] input Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect.
31 DIN[10] input Parallel LVCMOS data input with internal pulldown; active only in 12-bit mode and must be No Connect in 10-bit mode.
32 DIN[11] input Parallel LVCMOS data input with internal pulldown; active only in 12-bit mode and must be No Connect in 10-bit mode.
33 DAP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-32(5x5)
Category Interface
Pins 33

CAD (KiCad official)

  • Symbol: DS90UB633ARTVRQ1
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: WQFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: ds90ub633artvrq1-etched.step / ds90ub633artvrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub633artvrq1.step / ds90ub633artvrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (57 pp, sha256 ed2160e159cd9ab8, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF