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DS90UB633ARTVRQ1
Public Made by Adomby adom
Texas Instruments Serializers, Deserializers, WQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+70@@ -0,0 +1,70 @@+# DS90UB633ARTVRQ1++**Texas Instruments** · Serializers, Deserializers · WQFN-32(5x5)++DS90UB633ARTVRQ1 from Texas Instruments, in a WQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | HSYNC | input | Horizontal sync input with LVCMOS levels and internal pulldown; in 10-bit mode HS is restricted to no more than one transition per 10 PCLK cycles, and it may be left open if unused. |+| 2 | VSYNC | input | Vertical sync input with LVCMOS levels and internal pulldown; in 10-bit mode VS is restricted to no more than one transition per 10 PCLK cycles, and it may be left open if unused. |+| 3 | PCLK | input | Pixel clock input with LVCMOS levels and internal pulldown; the data strobe edge is set by register 0x03[0] (TRFB). |+| 4 | SCL | bidirectional | Clock line of the I2C-compatible bidirectional control bus, open-drain, requiring an external pullup resistor to V(VDDIO). |+| 5 | SDA | bidirectional | Data line of the I2C-compatible bidirectional control bus, open-drain, requiring an external pullup resistor to V(VDDIO). |+| 6 | IDX | input | Analog device ID address select; a resistor (RID) to ground and a 10-kΩ pullup to the 1.8 V rail set the serializer I2C device address per table 7-6. |+| 7 | RES | input | Reserved pin with LVCMOS levels and internal pulldown that MUST be tied LOW. |+| 8 | MODE | input | Analog device mode select; a resistor to ground and a 10-kΩ pullup to the 1.8 V rail select PCLK-from-imager or external-oscillator operation per table 7-2. |+| 9 | PDB | input | Power-down input with LVCMOS levels and internal pulldown; PDB = H enables the serializer, and PDB = L puts it in power-down with the PLL shut down and control register data not retained. |+| 10 | VDDPLL | power_in | Analog PLL power supply, 1.8 V ±5%. |+| 11 | VDDT | power_in | Analog Tx analog power supply, 1.8 V ±5%. |+| 12 | DOUT- | bidirectional | Inverting CML differential output and bidirectional control channel input; the interconnect must be AC-coupled with a 0.1-µF capacitor (0.047-µF in series with 50 Ω for single-ended coax). |+| 13 | DOUT+ | bidirectional | Non-inverting CML differential output and bidirectional control channel input; the interconnect must be AC-coupled with a 0.1-µF capacitor. |+| 14 | VDDCML | power_in | Analog CML and bidirectional channel driver power supply, 1.8 V ±5%. |+| 15 | GPO[0] | output | General-purpose LVCMOS output that follows GPIO[0] from the deserializer or the local serializer register; leave open if unused. |+| 16 | GPO[1] | output | General-purpose LVCMOS output that follows GPIO[1] from the deserializer or the local serializer register; leave open if unused. |+| 17 | GPO[2]/CLKOUT | output | General-purpose LVCMOS output (GPIO[2] or local register) that also serves as the divided-clock output in external oscillator mode; it is recommended to pull it to GND with at least 40 kΩ to ensure LOW when PDB rises. |+| 18 | GPO[3]/CLKIN | bidirectional | General-purpose LVCMOS input/output (GPIO[3] or local register) that serves as the external oscillator clock input in external oscillator mode; leave open if unused. |+| 19 | DIN[0] | input | Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect. |+| 20 | DIN[1] | input | Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect. |+| 21 | DIN[2] | input | Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect. |+| 22 | DIN[3] | input | Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect. |+| 23 | DIN[4] | input | Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect. |+| 24 | DIN[5] | input | Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect. |+| 25 | VDDIO | power_in | I/O stage power supply for the single-ended inputs, SDA and SCL; may be 1.8 V ±5%, 2.8 V ±10%, or 3.3 V ±10%. |+| 26 | DIN[6] | input | Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect. |+| 27 | DIN[7] | input | Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect. |+| 28 | VDDD | power_in | Digital core power supply, 1.8 V ±5%. |+| 29 | DIN[8] | input | Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect. |+| 30 | DIN[9] | input | Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect. |+| 31 | DIN[10] | input | Parallel LVCMOS data input with internal pulldown; active only in 12-bit mode and must be No Connect in 10-bit mode. |+| 32 | DIN[11] | input | Parallel LVCMOS data input with internal pulldown; active only in 12-bit mode and must be No Connect in 10-bit mode. |+| 33 | DAP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-32(5x5) |+| Category | Interface |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `DS90UB633ARTVRQ1`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: WQFN-32(5x5) (KiCad packages3D, STEP)+- 3D model files: `ds90ub633artvrq1-etched.step` / `ds90ub633artvrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds90ub633artvrq1.step` / `ds90ub633artvrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds90ub633a-q1) (57 pp, sha256 `ed2160e159cd9ab8`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ds90ub633artvrq1-datasheet.pdf)
page.jsonadded+351@@ -0,0 +1,351 @@+{+ "slug": "ds90ub633artvrq1",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Serializers, Deserializers, WQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "ds90ub633artvrq1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ds90ub633artvrq1.kicad_sym",+ "ds90ub633artvrq1.kicad_mod",+ "ds90ub633artvrq1.glb",+ "ds90ub633artvrq1.step",+ "ds90ub633artvrq1.lbr",+ "docs/hero.png",+ "docs/ds90ub633artvrq1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ds90ub633artvrq1-hero.glb",+ "ds90ub633artvrq1-hero.overlay.json"+ ],+ "component": {+ "mpn": "DS90UB633ARTVRQ1",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-32(5x5)",+ "pin_count": 33,+ "category": "Interface",+ "subcategory": "Serializers, Deserializers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ds90ub633a-q1",+ "parts": {+ "symbol": "ds90ub633artvrq1.kicad_sym",+ "footprint": "ds90ub633artvrq1.kicad_mod",+ "model_3d": "ds90ub633artvrq1-hero.glb",+ "model_3d_plain": "ds90ub633artvrq1.glb",+ "model_3d_step": "ds90ub633artvrq1-etched.step",+ "model_3d_step_plain": "ds90ub633artvrq1.step",+ "lbr": "ds90ub633artvrq1.lbr"+ },+ "distributor_links": {+ "lcsc": "C3189325",+ "digikey": "296-DS90UB633ARTVRQ1TR-ND",+ "mouser": "595-DS90UB633ARTVRQ1"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T18:06:05Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-DS90UB633ARTVRQ1TR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DS90UB633ARTVRQ1",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "HSYNC",+ "type": "input",+ "description": "Horizontal sync input with LVCMOS levels and internal pulldown; in 10-bit mode HS is restricted to no more than one transition per 10 PCLK cycles, and it may be left open if unused."+ },+ {+ "number": "2",+ "name": "VSYNC",+ "type": "input",+ "description": "Vertical sync input with LVCMOS levels and internal pulldown; in 10-bit mode VS is restricted to no more than one transition per 10 PCLK cycles, and it may be left open if unused."+ },+ {+ "number": "3",+ "name": "PCLK",+ "type": "input",+ "description": "Pixel clock input with LVCMOS levels and internal pulldown; the data strobe edge is set by register 0x03[0] (TRFB)."+ },+ {+ "number": "4",+ "name": "SCL",+ "type": "bidirectional",+ "description": "Clock line of the I2C-compatible bidirectional control bus, open-drain, requiring an external pullup resistor to V(VDDIO)."+ },+ {+ "number": "5",+ "name": "SDA",+ "type": "bidirectional",+ "description": "Data line of the I2C-compatible bidirectional control bus, open-drain, requiring an external pullup resistor to V(VDDIO)."+ },+ {+ "number": "6",+ "name": "IDX",+ "type": "input",+ "description": "Analog device ID address select; a resistor (RID) to ground and a 10-kΩ pullup to the 1.8 V rail set the serializer I2C device address per table 7-6."+ },+ {+ "number": "7",+ "name": "RES",+ "type": "input",+ "description": "Reserved pin with LVCMOS levels and internal pulldown that MUST be tied LOW."+ },+ {+ "number": "8",+ "name": "MODE",+ "type": "input",+ "description": "Analog device mode select; a resistor to ground and a 10-kΩ pullup to the 1.8 V rail select PCLK-from-imager or external-oscillator operation per table 7-2."+ },+ {+ "number": "9",+ "name": "PDB",+ "type": "input",+ "description": "Power-down input with LVCMOS levels and internal pulldown; PDB = H enables the serializer, and PDB = L puts it in power-down with the PLL shut down and control register data not retained."+ },+ {+ "number": "10",+ "name": "VDDPLL",+ "type": "power_in",+ "description": "Analog PLL power supply, 1.8 V ±5%."+ },+ {+ "number": "11",+ "name": "VDDT",+ "type": "power_in",+ "description": "Analog Tx analog power supply, 1.8 V ±5%."+ },+ {+ "number": "12",+ "name": "DOUT-",+ "type": "bidirectional",+ "description": "Inverting CML differential output and bidirectional control channel input; the interconnect must be AC-coupled with a 0.1-µF capacitor (0.047-µF in series with 50 Ω for single-ended coax)."+ },+ {+ "number": "13",+ "name": "DOUT+",+ "type": "bidirectional",+ "description": "Non-inverting CML differential output and bidirectional control channel input; the interconnect must be AC-coupled with a 0.1-µF capacitor."+ },+ {+ "number": "14",+ "name": "VDDCML",+ "type": "power_in",+ "description": "Analog CML and bidirectional channel driver power supply, 1.8 V ±5%."+ },+ {+ "number": "15",+ "name": "GPO[0]",+ "type": "output",+ "description": "General-purpose LVCMOS output that follows GPIO[0] from the deserializer or the local serializer register; leave open if unused."+ },+ {+ "number": "16",+ "name": "GPO[1]",+ "type": "output",+ "description": "General-purpose LVCMOS output that follows GPIO[1] from the deserializer or the local serializer register; leave open if unused."+ },+ {+ "number": "17",+ "name": "GPO[2]/CLKOUT",+ "type": "output",+ "description": "General-purpose LVCMOS output (GPIO[2] or local register) that also serves as the divided-clock output in external oscillator mode; it is recommended to pull it to GND with at least 40 kΩ to ensure LOW when PDB rises."+ },+ {+ "number": "18",+ "name": "GPO[3]/CLKIN",+ "type": "bidirectional",+ "description": "General-purpose LVCMOS input/output (GPIO[3] or local register) that serves as the external oscillator clock input in external oscillator mode; leave open if unused."+ },+ {+ "number": "19",+ "name": "DIN[0]",+ "type": "input",+ "description": "Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect."+ },+ {+ "number": "20",+ "name": "DIN[1]",+ "type": "input",+ "description": "Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect."+ },+ {+ "number": "21",+ "name": "DIN[2]",+ "type": "input",+ "description": "Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect."+ },+ {+ "number": "22",+ "name": "DIN[3]",+ "type": "input",+ "description": "Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect."+ },+ {+ "number": "23",+ "name": "DIN[4]",+ "type": "input",+ "description": "Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect."+ },+ {+ "number": "24",+ "name": "DIN[5]",+ "type": "input",+ "description": "Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect."+ },+ {+ "number": "25",+ "name": "VDDIO",+ "type": "power_in",+ "description": "I/O stage power supply for the single-ended inputs, SDA and SCL; may be 1.8 V ±5%, 2.8 V ±10%, or 3.3 V ±10%."+ },+ {+ "number": "26",+ "name": "DIN[6]",+ "type": "input",+ "description": "Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect."+ },+ {+ "number": "27",+ "name": "DIN[7]",+ "type": "input",+ "description": "Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect."+ },+ {+ "number": "28",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital core power supply, 1.8 V ±5%."+ },+ {+ "number": "29",+ "name": "DIN[8]",+ "type": "input",+ "description": "Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect."+ },+ {+ "number": "30",+ "name": "DIN[9]",+ "type": "input",+ "description": "Parallel LVCMOS data input with internal pulldown, active in both 10-bit and 12-bit modes; unused inputs must be No Connect."+ },+ {+ "number": "31",+ "name": "DIN[10]",+ "type": "input",+ "description": "Parallel LVCMOS data input with internal pulldown; active only in 12-bit mode and must be No Connect in 10-bit mode."+ },+ {+ "number": "32",+ "name": "DIN[11]",+ "type": "input",+ "description": "Parallel LVCMOS data input with internal pulldown; active only in 12-bit mode and must be No Connect in 10-bit mode."+ },+ {+ "number": "33",+ "name": "DAP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package and MPN mapping: the MPN DS90UB633ARTVRQ1 is the RTV (WQFN-32, 5x5 mm) package, ordered as 1; DIN[0:11] bit-to-pin mapping is inferred. The datasheet lists the pin numbers 19,20,21,22,23,24,26,2; GPO[1:0] pin mapping is inferred from the grouped pin list '16,15' for GPO[1:0]; GPO[1] = 16 and GPO",+ "exposed pad 33 added from the footprint"+ ],+ "pages_sent": 25,+ "cost_usd": 0.1536,+ "at": "2026-10-08T18:05:20"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ds90ub633a-q1",+ "pages": 57,+ "sha256": "ed2160e159cd9ab8",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ds90ub633artvrq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.875+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "5fa713ea46b36980895812ed853577889b7cb06d275041a39b99bc0be305dc79",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ds90ub633artvrq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.875+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "47e6f83baa0337691306ed6f30ff7300ce06cc9342d28056a0e225677d3635c7",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}