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DS90LV804TSQ

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Texas Instruments LVDS ICs, WQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS90LV804TSQ

Texas Instruments · LVDS ICs · WQFN-32(5x5)

DS90LV804TSQ from Texas Instruments, in a WQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference for LVDS and CMOS circuitry; the DAP is the primary ground connection, so this pin should also be tied to ground for proper biasing.
2 GND power_in Ground reference for LVDS and CMOS circuitry; the DAP is the primary ground connection, so this pin should also be tied to ground for proper biasing.
3 VDD power_in Power supply pin, VDD = 3.3V ±5% (recommended supply 3.15V to 3.45V).
4 VDD power_in Power supply pin, VDD = 3.3V ±5% (recommended supply 3.15V to 3.45V).
5 GND power_in Ground reference for LVDS and CMOS circuitry; the DAP is the primary ground connection, so this pin should also be tied to ground for proper biasing.
6 VDD power_in Power supply pin, VDD = 3.3V ±5% (recommended supply 3.15V to 3.45V).
7 VDD power_in Power supply pin, VDD = 3.3V ±5% (recommended supply 3.15V to 3.45V).
8 EN input LVTTL/LVCMOS enable input: when LOW the driver is disabled and the LVDS outputs and internal bias are in TRI-STATE, and when HIGH the driver is enabled.
9 IN0+ input Channel 0 non-inverting LVDS differential input, internally terminated with 100Ω across IN0+ and IN0−.
10 IN0- input Channel 0 inverting LVDS differential input, internally terminated with 100Ω across IN0+ and IN0−.
11 IN1+ input Channel 1 non-inverting LVDS differential input, internally terminated with 100Ω across IN1+ and IN1−.
12 IN1- input Channel 1 inverting LVDS differential input, internally terminated with 100Ω across IN1+ and IN1−.
13 IN2+ input Channel 2 non-inverting LVDS differential input, internally terminated with 100Ω across IN2+ and IN2−.
14 IN2- input Channel 2 inverting LVDS differential input, internally terminated with 100Ω across IN2+ and IN2−.
15 IN3+ input Channel 3 non-inverting LVDS differential input, internally terminated with 100Ω across IN3+ and IN3−.
16 IN3- input Channel 3 inverting LVDS differential input, internally terminated with 100Ω across IN3+ and IN3−.
17 GND power_in Ground reference for LVDS and CMOS circuitry; the DAP is the primary ground connection, so this pin should also be tied to ground for proper biasing.
18 GND power_in Ground reference for LVDS and CMOS circuitry; the DAP is the primary ground connection, so this pin should also be tied to ground for proper biasing.
19 VDD power_in Power supply pin, VDD = 3.3V ±5% (recommended supply 3.15V to 3.45V).
20 VDD power_in Power supply pin, VDD = 3.3V ±5% (recommended supply 3.15V to 3.45V).
21 VDD power_in Power supply pin, VDD = 3.3V ±5% (recommended supply 3.15V to 3.45V).
22 VDD power_in Power supply pin, VDD = 3.3V ±5% (recommended supply 3.15V to 3.45V).
23 N/C unconnected No connect; leave unconnected.
24 N/C unconnected No connect; leave unconnected.
25 OUT3- output Channel 3 inverting LVDS differential output, optimized for point-to-point backplane and cable use (not multidrop/BLVDS).
26 OUT3+ output Channel 3 non-inverting LVDS differential output, optimized for point-to-point backplane and cable use (not multidrop/BLVDS).
27 OUT2- output Channel 2 inverting LVDS differential output, optimized for point-to-point backplane and cable use (not multidrop/BLVDS).
28 OUT2+ output Channel 2 non-inverting LVDS differential output, optimized for point-to-point backplane and cable use (not multidrop/BLVDS).
29 OUT1- output Channel 1 inverting LVDS differential output, optimized for point-to-point backplane and cable use (not multidrop/BLVDS).
30 OUT1+ output Channel 1 non-inverting LVDS differential output, optimized for point-to-point backplane and cable use (not multidrop/BLVDS).
31 OUT0- output Channel 0 inverting LVDS differential output, optimized for point-to-point backplane and cable use (not multidrop/BLVDS).
32 OUT0+ output Channel 0 non-inverting LVDS differential output, optimized for point-to-point backplane and cable use (not multidrop/BLVDS).
33 DAP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-32(5x5)
Category Interface
Pins 33

CAD (KiCad official)

  • Symbol: DS90LV804TSQ
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: WQFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: ds90lv804tsq-etched.step / ds90lv804tsq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90lv804tsq.step / ds90lv804tsq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 b77cddb0306e6ff1, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF