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DS90LV048ATMX

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Texas Instruments LVDS ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs ds90lv048atmx: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers ds90lv048atmx: viewers · Ray
ds90lv048atmx-etched.fit.json ds90lv048atmx: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ds90lv048atmx-etched.glb ds90lv048atmx: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ds90lv048atmx-etched.step ds90lv048atmx: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ds90lv048atmx.glb Publish 0.1.0 · Ray
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ds90lv048atmx.step Publish 0.1.0 · Ray
package.json ds90lv048atmx: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json ds90lv048atmx: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/ds90lv048atmx · Ray

DS90LV048ATMX

Texas Instruments · LVDS ICs · SOIC-16

DS90LV048ATMX from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RIN1- input Inverting LVDS differential receiver input for channel 1; receiver input voltage range GND to 3 V, differential threshold region −100 mV to 0 mV, common-mode range 0.1 V to 2.3 V.
2 RIN1+ input Noninverting LVDS differential receiver input for channel 1; receiver input voltage range GND to 3 V, differential threshold region −100 mV to 0 mV, common-mode range 0.1 V to 2.3 V.
3 RIN2+ input Noninverting LVDS differential receiver input for channel 2; receiver input voltage range GND to 3 V, differential threshold region −100 mV to 0 mV, common-mode range 0.1 V to 2.3 V.
4 RIN2- input Inverting LVDS differential receiver input for channel 2; receiver input voltage range GND to 3 V, differential threshold region −100 mV to 0 mV, common-mode range 0.1 V to 2.3 V.
5 RIN3- input Inverting LVDS differential receiver input for channel 3; receiver input voltage range GND to 3 V, differential threshold region −100 mV to 0 mV, common-mode range 0.1 V to 2.3 V.
6 RIN3+ input Noninverting LVDS differential receiver input for channel 3; receiver input voltage range GND to 3 V, differential threshold region −100 mV to 0 mV, common-mode range 0.1 V to 2.3 V.
7 RIN4+ input Noninverting LVDS differential receiver input for channel 4; receiver input voltage range GND to 3 V, differential threshold region −100 mV to 0 mV, common-mode range 0.1 V to 2.3 V.
8 RIN4- input Inverting LVDS differential receiver input for channel 4; receiver input voltage range GND to 3 V, differential threshold region −100 mV to 0 mV, common-mode range 0.1 V to 2.3 V.
9 EN* input Active-low receiver enable, ANDed with EN; when high the receiver is disabled and all outputs are TRI-STATE; receiver is enabled when this pin is low or open and EN is high; VIH min 2 V, VIL max 0.8 V.
10 ROUT4 tri_state 3-V CMOS TRI-STATE output for channel 4; VOH min 2.7 V at IOH = −0.4 mA, VOL max 0.25 V at IOL = 2 mA; output is high-impedance when disabled.
11 ROUT3 tri_state 3-V CMOS TRI-STATE output for channel 3; VOH min 2.7 V at IOH = −0.4 mA, VOL max 0.25 V at IOL = 2 mA; output is high-impedance when disabled.
12 GND power_in Ground reference pin.
13 VCC power_in Power supply pin; +3.3 V ±0.3 V (3.0 V min, 3.6 V max); bypass with 0.1-µF and 0.001-µF ceramic capacitors in parallel at pin.
14 ROUT2 tri_state 3-V CMOS TRI-STATE output for channel 2; VOH min 2.7 V at IOH = −0.4 mA, VOL max 0.25 V at IOL = 2 mA; output is high-impedance when disabled.
15 ROUT1 tri_state 3-V CMOS TRI-STATE output for channel 1; VOH min 2.7 V at IOH = −0.4 mA, VOL max 0.25 V at IOL = 2 mA; output is high-impedance when disabled.
16 EN input Active-high receiver enable, ANDed with EN*; when low the receiver is disabled and all outputs are TRI-STATE; receiver is enabled when this pin is high and EN* is low or open; VIH min 2 V, VIL max 0.8 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Interface
Pins 16

CAD (KiCad official)

  • Symbol: DS90LV048ATMX
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ds90lv048atmx-etched.step / ds90lv048atmx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90lv048atmx.step / ds90lv048atmx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 65b8bc4088696d56, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF